From 0f9ef0ea718b9d52ac6724618a179ac7d83ade65 Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Fri, 8 Aug 2025 09:07:42 -0400 Subject: [PATCH] nouveau/push: Rename push_method to push_mthd The trait is Mthd so this is more consistant. It's also shorter. Reviewed-by: Mel Henning Part-of: --- src/nouveau/compiler/nak/hw_runner.rs | 26 +++++++++++++------------- src/nouveau/compiler/nak/hw_tests.rs | 20 ++++++++++---------- src/nouveau/headers/nv_push_rs/lib.rs | 4 ++-- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/nouveau/compiler/nak/hw_runner.rs b/src/nouveau/compiler/nak/hw_runner.rs index f8a14142978..1671db980de 100644 --- a/src/nouveau/compiler/nak/hw_runner.rs +++ b/src/nouveau/compiler/nak/hw_runner.rs @@ -522,15 +522,15 @@ impl Runner { // Fill out the pushbuf let mut p = NvPush::new(); - p.push_method(cla0c0::SetObject { + p.push_mthd(cla0c0::SetObject { class_id: self.dev_info().cls_compute.into(), engine_id: 0, }); if self.dev_info().cls_compute < VOLTA_COMPUTE_A { - p.push_method(cla0c0::SetProgramRegionA { + p.push_mthd(cla0c0::SetProgramRegionA { address_upper: (bo.addr >> 32) as u32, }); - p.push_method(cla0c0::SetProgramRegionB { + p.push_mthd(cla0c0::SetProgramRegionB { address_lower: bo.addr as u32, }); } @@ -543,41 +543,41 @@ impl Runner { let lmem_base_addr = 0xff000000_u32; if self.dev_info().cls_compute >= VOLTA_COMPUTE_A { - p.push_method(clc3c0::SetShaderSharedMemoryWindowA { + p.push_mthd(clc3c0::SetShaderSharedMemoryWindowA { base_address_upper: (smem_base_addr >> 32) as u32, }); - p.push_method(clc3c0::SetShaderSharedMemoryWindowB { + p.push_mthd(clc3c0::SetShaderSharedMemoryWindowB { base_address: smem_base_addr as u32, }); - p.push_method(clc3c0::SetShaderLocalMemoryWindowA { + p.push_mthd(clc3c0::SetShaderLocalMemoryWindowA { base_address_upper: 0, }); - p.push_method(clc3c0::SetShaderLocalMemoryWindowB { + p.push_mthd(clc3c0::SetShaderLocalMemoryWindowB { base_address: lmem_base_addr, }); } else { - p.push_method(cla0c0::SetShaderSharedMemoryWindow { + p.push_mthd(cla0c0::SetShaderSharedMemoryWindow { base_address: smem_base_addr as u32, }); - p.push_method(cla0c0::SetShaderLocalMemoryWindow { + p.push_mthd(cla0c0::SetShaderLocalMemoryWindow { base_address: lmem_base_addr, }); } if self.dev_info().cls_compute >= MAXWELL_COMPUTE_B { - p.push_method(clb1c0::InvalidateSkedCaches { v: 0 }); + p.push_mthd(clb1c0::InvalidateSkedCaches { v: 0 }); } - p.push_method(cla0c0::SendPcasA { + p.push_mthd(cla0c0::SendPcasA { qmd_address_shifted8: (qmd.addr >> 8) as u32, }); if self.dev_info().cls_compute >= AMPERE_COMPUTE_A { - p.push_method(clc6c0::SendSignalingPcas2B { + p.push_mthd(clc6c0::SendSignalingPcas2B { pcas_action: clc6c0::SendSignalingPcas2BPcasAction::InvalidateCopySchedule, }); } else { - p.push_method(cla0c0::SendSignalingPcasB { + p.push_mthd(cla0c0::SendSignalingPcasB { invalidate: true, schedule: true, }); diff --git a/src/nouveau/compiler/nak/hw_tests.rs b/src/nouveau/compiler/nak/hw_tests.rs index 09e4a0744de..883ab733da5 100644 --- a/src/nouveau/compiler/nak/hw_tests.rs +++ b/src/nouveau/compiler/nak/hw_tests.rs @@ -1871,24 +1871,24 @@ fn test_render_enable() -> io::Result<()> { let mut p = NvPush::new(); let in_gpu_addr = bo.addr + in_offset; - p.push_method(cl90b5::SetRenderEnableA { + p.push_mthd(cl90b5::SetRenderEnableA { upper: (in_gpu_addr >> 32) as u32, }); - p.push_method(cl90b5::SetRenderEnableB { + p.push_mthd(cl90b5::SetRenderEnableB { lower: in_gpu_addr as u32, }); - p.push_method(cl90b5::SetRenderEnableC { mode }); + p.push_mthd(cl90b5::SetRenderEnableC { mode }); let out_gpu_addr = bo.addr + out_offset; - p.push_method(cl90b5::OffsetOutUpper { + p.push_mthd(cl90b5::OffsetOutUpper { upper: (out_gpu_addr >> 32) as u32, }); - p.push_method(cl90b5::OffsetOutLower { + p.push_mthd(cl90b5::OffsetOutLower { value: out_gpu_addr as u32, }); - p.push_method(cl90b5::LineLengthIn { value: 1 }); - p.push_method(cl90b5::SetRemapConstA { v: WRITE_VAL }); - p.push_method(cl90b5::SetRemapComponents { + p.push_mthd(cl90b5::LineLengthIn { value: 1 }); + p.push_mthd(cl90b5::SetRemapConstA { v: WRITE_VAL }); + p.push_mthd(cl90b5::SetRemapComponents { component_size: cl90b5::SetRemapComponentsComponentSize::Four, dst_x: cl90b5::SetRemapComponentsDstX::ConstA, dst_y: cl90b5::SetRemapComponentsDstY::NoWrite, @@ -1897,7 +1897,7 @@ fn test_render_enable() -> io::Result<()> { num_src_components: cl90b5::SetRemapComponentsNumSrcComponents::One, num_dst_components: cl90b5::SetRemapComponentsNumDstComponents::One, }); - p.push_method(cl90b5::LaunchDma { + p.push_mthd(cl90b5::LaunchDma { data_transfer_type: cl90b5::LaunchDmaDataTransferType::NonPipelined, flush_enable: true, semaphore_type: cl90b5::LaunchDmaSemaphoreType::None, @@ -1908,7 +1908,7 @@ fn test_render_enable() -> io::Result<()> { remap_enable: true, }); - p.push_method(cl90b5::SetRenderEnableC { + p.push_mthd(cl90b5::SetRenderEnableC { mode: cl90b5::SetRenderEnableCMode::True, }); diff --git a/src/nouveau/headers/nv_push_rs/lib.rs b/src/nouveau/headers/nv_push_rs/lib.rs index 077358fbaee..ac7adcbbdfe 100644 --- a/src/nouveau/headers/nv_push_rs/lib.rs +++ b/src/nouveau/headers/nv_push_rs/lib.rs @@ -193,7 +193,7 @@ impl Push { } } - pub fn push_method(&mut self, mthd: M) { + pub fn push_mthd(&mut self, mthd: M) { self.push_mthd_bits(class_to_subc(M::CLASS), M::ADDR, mthd.to_bits()); } @@ -222,7 +222,7 @@ impl Push { self.mem.push(mthd.to_bits()); } - pub fn push_array_method(&mut self, i: usize, mthd: M) { + pub fn push_array_mthd(&mut self, i: usize, mthd: M) { self.push_mthd_bits( class_to_subc(M::CLASS), M::addr(i),