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freedreno: Name a few events

Browse source 
And add them to the gpu_event helper so we don't need to open-code these
packets.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37009>
This commit is contained in:
Rob Clark 2025-08-25 08:03:28 -07:00 • committed by Marge Bot
parent 77c42c1a57
commit 0f2f247f91
7 changed files with 25 additions and 22 deletions
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9
src/freedreno/common/freedreno_gpu_event.h
View file

@ -43,6 +43,9 @@ enum fd_gpu_event : uint32_t {
FD_CCU_CLEAN_COLOR,
FD_LRZ_CLEAR,
FD_LRZ_FLUSH,
FD_LRZ_INVALIDATE,
FD_VSC_BINNING_START,
FD_VSC_BINNING_END,
FD_BLIT,
FD_LABEL,
FD_DUMMY_EVENT,
@ -82,6 +85,9 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events<A6XX>[FD_GPU_EVENT_MAX]
{PC_CCU_FLUSH_COLOR_TS, true}, /* FD_CCU_CLEAN_COLOR */
{LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */
{LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */
{LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */
{VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */
{VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */
{BLIT, false}, /* FD_BLIT */
{LABEL, false}, /* FD_LABEL */
};
@ -110,6 +116,9 @@ constexpr inline struct fd_gpu_event_info fd_gpu_events<A7XX>[FD_GPU_EVENT_MAX]
{CCU_CLEAN_COLOR, false}, /* FD_CCU_CLEAN_COLOR */
{LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */
{LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */
{LRZ_CACHE_INVALIDATE, false}, /* FD_LRZ_INVALIDATE */
{VSC_BINNING_START, false}, /* FD_VSC_BINNING_START */
{VSC_BINNING_END, false}, /* FD_VSC_BINNING_END */
{BLIT, false}, /* FD_BLIT */
{LABEL, false}, /* FD_LABEL */
{DUMMY_EVENT, false}, /* FD_DUMMY_EVENT */

6
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -120,12 +120,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
<value name="UNK_40" value="40" variants="A7XX"/>
<value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/>
<value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/>
<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
<value name="UNK_2C" value="44" variants="A5XX-"/>
<value name="UNK_2D" value="45" variants="A5XX-"/>
<value name="VSC_BINNING_START" value="44" variants="A5XX-"/>
<value name="VSC_BINNING_END" value="45" variants="A5XX-"/>
<!-- a6xx events -->
<doc>

8
src/freedreno/tests/reference/fd-clouds.log
View file

@ -418,8 +418,8 @@ cmdstream[0]: 1023 dwords
VFD_POWER_CNTL: 0x1
0000000001d914a0: 0000: 40a0f801 00000001
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = UNK_2C }
event UNK_2C
{ EVENT = VSC_BINNING_START }
event VSC_BINNING_START
0000000001d914a8: 0000: 70460001 0000002c
write RB_WINDOW_OFFSET (8890)
RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
@ -1139,8 +1139,8 @@ cmdstream[0]: 1023 dwords
{ [0].ADDR = 0 }
0000000001d914e8: 0000: 70438003 00040000 00000000 00000000
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = UNK_2D }
event UNK_2D
{ EVENT = VSC_BINNING_END }
event VSC_BINNING_END
0000000001d914f8: 0000: 70460001 0000002d
opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = CACHE_INVALIDATE }

8
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1947,7 +1947,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_COLOR);
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_DEPTH);
tu_emit_raw_event_write<CHIP>(cmd, cs, UNK_40, false);
tu_emit_event_write<CHIP>(cmd, cs, FD_LRZ_INVALIDATE);
tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
tu_cs_emit_wfi(cs);
}
@ -2189,8 +2189,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
}
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, UNK_2C);
tu_emit_event_write<CHIP>(cmd, cs, FD_VSC_BINNING_START);
tu_cs_emit_regs(cs,
A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
@ -2219,8 +2218,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, UNK_2D);
tu_emit_event_write<CHIP>(cmd, cs, FD_VSC_BINNING_END);
/* This flush is probably required because the VSC, which produces the
* visibility stream, is a client of UCHE, whereas the CP needs to read the

4
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
View file

@ -350,7 +350,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
OUT_RING(ring, A5XX_VPC_MODE_CNTL_BINNING_PASS);
fd5_event_write(batch, ring, UNK_2C, false);
fd5_event_write(batch, ring, VSC_BINNING_START, false);
OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) | A5XX_RB_WINDOW_OFFSET_Y(0));
@ -360,7 +360,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
fd_reset_wfi(batch);
fd5_event_write(batch, ring, UNK_2D, false);
fd5_event_write(batch, ring, VSC_BINNING_END, false);
fd5_event_write(batch, ring, CACHE_FLUSH_TS, true);

6
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -1099,11 +1099,9 @@ fd6_emit_restore(fd_cs &cs, struct fd_batch *batch)
fd6_event_write<CHIP>(ctx, cs, FD_CCU_INVALIDATE_COLOR);
fd6_event_write<CHIP>(ctx, cs, FD_CCU_INVALIDATE_DEPTH);
fd_pkt7(cs, CP_EVENT_WRITE, 1)
.add(UNK_40);
fd6_event_write<CHIP>(ctx, cs, FD_LRZ_INVALIDATE);
fd6_event_write<CHIP>(ctx, cs, FD_CACHE_INVALIDATE);
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
}

6
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -969,8 +969,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
.add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
}
fd_pkt7(cs, CP_EVENT_WRITE, 1)
.add(UNK_2C);
fd6_event_write<CHIP>(batch->ctx, cs, FD_VSC_BINNING_START);
fd_crb(cs, 2)
.add(A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0))
@ -988,8 +987,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
.add(CP_SET_DRAW_STATE__0(0, .disable_all_groups = true))
.add(CP_SET_DRAW_STATE__ADDR(0));
fd_pkt7(cs, CP_EVENT_WRITE, 1)
.add(UNK_2D);
fd6_event_write<CHIP>(batch->ctx, cs, FD_VSC_BINNING_END);
/* This flush is probably required because the VSC, which produces the
* visibility stream, is a client of UCHE, whereas the CP needs to read