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https://gitlab.freedesktop.org/mesa/mesa.git
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i965: Add support for GL_AMD_performance_monitor on Ironlake.
Ironlake's counters are always enabled; userspace can simply send a
MI_REPORT_PERF_COUNT packet to take a snapshot of them. This makes it
easy to implement.
The counters are documented in the source code for the intel-gpu-tools
intel_perf_counters utility.
v2: Adjust for core data structure changes. Add a table mapping buffer
object offsets to exposed counters (which changes each generation).
Finally, add report ID assertions to sanity check the BO layout
(thanks to Carl Worth).
v3: Update for core BeginPerfMonitor hook changes (requested by Brian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Kenneth Graunke
parent
b2e327e08f
commit
0f2da77307
6 changed files with 420 additions and 0 deletions
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@ -69,6 +69,7 @@ i965_FILES = \
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brw_lower_texture_gradients.cpp \
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brw_misc_state.c \
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brw_object_purgeable.c \
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brw_performance_monitor.c \
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brw_program.c \
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brw_primitive_restart.c \
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brw_queryobj.c \
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@ -503,6 +503,10 @@ brwCreateContext(int api,
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_mesa_initialize_dispatch_tables(ctx);
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_mesa_initialize_vbo_vtxfmt(ctx);
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if (ctx->Extensions.AMD_performance_monitor) {
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brw_init_performance_monitors(brw);
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}
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return true;
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}
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@ -128,6 +128,7 @@ struct brw_vs_prog_key;
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struct brw_vec4_prog_key;
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struct brw_wm_prog_key;
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struct brw_wm_prog_data;
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struct brw_perf_bo_layout;
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enum brw_state_id {
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BRW_STATE_URB_FENCE,
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@ -1313,6 +1314,16 @@ struct brw_context
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bool begin_emitted;
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} query;
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struct {
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/* A map describing which counters are stored at a particular 32-bit
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* offset in the buffer object.
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*/
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const struct brw_perf_bo_layout *bo_layout;
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/* Number of 32-bit entries in the buffer object. */
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int entries_in_bo;
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} perfmon;
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int num_atoms;
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const struct brw_tracked_state **atoms;
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@ -1485,6 +1496,9 @@ bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
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bool brw_render_target_supported(struct brw_context *brw,
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struct gl_renderbuffer *rb);
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/* brw_performance_monitor.c */
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void brw_init_performance_monitors(struct brw_context *brw);
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/* gen6_sol.c */
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void
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brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
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@ -1817,6 +1817,13 @@ enum brw_wm_barycentric_interp_mode {
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#define CMD_MI_FLUSH 0x0200
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#define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
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/* DW0 */
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# define GEN5_MI_COUNTER_SET_0 (0 << 6)
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# define GEN5_MI_COUNTER_SET_1 (1 << 6)
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/* DW1 */
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# define MI_COUNTER_ADDRESS_GTT (1 << 0)
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/* DW2: a user-defined report ID (written to the buffer but can be anything) */
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/* Bitfields for the URB_WRITE message, DW2 of message header: */
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#define URB_WRITE_PRIM_END 0x1
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391
src/mesa/drivers/dri/i965/brw_performance_monitor.c
Normal file
391
src/mesa/drivers/dri/i965/brw_performance_monitor.c
Normal file
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@ -0,0 +1,391 @@
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* \file brw_performance_monitor.c
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*
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* Implementation of the GL_AMD_performance_monitor extension.
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*
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* Currently only for Ironlake.
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*/
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#include <limits.h>
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#include "main/bitset.h"
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#include "main/macros.h"
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#include "main/mtypes.h"
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#include "main/performance_monitor.h"
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#include "brw_context.h"
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#include "brw_defines.h"
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#include "intel_batchbuffer.h"
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/**
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* i965 representation of a performance monitor object.
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*/
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struct brw_perf_monitor_object
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{
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/** The base class. */
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struct gl_perf_monitor_object base;
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/**
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* BO containing raw counter data in a hardware specific form.
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*/
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drm_intel_bo *bo;
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};
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/** Downcasting convenience macro. */
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static inline struct brw_perf_monitor_object *
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brw_perf_monitor(struct gl_perf_monitor_object *m)
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{
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return (struct brw_perf_monitor_object *) m;
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}
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#define SECOND_SNAPSHOT_OFFSET_IN_BYTES 2048
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/* Two random values used to ensure we're getting valid snapshots. */
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#define FIRST_SNAPSHOT_REPORT_ID 0xd2e9c607
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#define SECOND_SNAPSHOT_REPORT_ID 0xad584b1d
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/******************************************************************************/
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#define COUNTER(name) \
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{ \
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.Name = name, \
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.Type = GL_UNSIGNED_INT, \
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.Minimum = { .u32 = 0 }, \
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.Maximum = { .u32 = ~0 }, \
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}
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#define GROUP(name, max_active, counter_list) \
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{ \
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.Name = name, \
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.MaxActiveCounters = max_active, \
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.Counters = counter_list, \
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.NumCounters = ARRAY_SIZE(counter_list), \
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}
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struct brw_perf_bo_layout {
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int group;
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int counter;
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};
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/**
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* Ironlake:
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* @{
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*/
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const static struct gl_perf_monitor_counter gen5_raw_aggregating_counters[] = {
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COUNTER("cycles the CS unit is starved"),
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COUNTER("cycles the CS unit is stalled"),
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COUNTER("cycles the VF unit is starved"),
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COUNTER("cycles the VF unit is stalled"),
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COUNTER("cycles the VS unit is starved"),
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COUNTER("cycles the VS unit is stalled"),
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COUNTER("cycles the GS unit is starved"),
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COUNTER("cycles the GS unit is stalled"),
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COUNTER("cycles the CL unit is starved"),
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COUNTER("cycles the CL unit is stalled"),
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COUNTER("cycles the SF unit is starved"),
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COUNTER("cycles the SF unit is stalled"),
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COUNTER("cycles the WZ unit is starved"),
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COUNTER("cycles the WZ unit is stalled"),
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COUNTER("Z buffer read/write"),
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COUNTER("cycles each EU was active"),
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COUNTER("cycles each EU was suspended"),
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COUNTER("cycles threads loaded all EUs"),
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COUNTER("cycles filtering active"),
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COUNTER("cycles PS threads executed"),
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COUNTER("subspans written to RC"),
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COUNTER("bytes read for texture reads"),
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COUNTER("texels returned from sampler"),
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COUNTER("polygons not culled"),
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COUNTER("clocks MASF has valid message"),
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COUNTER("64b writes/reads from RC"),
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COUNTER("reads on dataport"),
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COUNTER("clocks MASF has valid msg not consumed by sampler"),
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COUNTER("cycles any EU is stalled for math"),
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};
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const static struct gl_perf_monitor_group gen5_groups[] = {
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GROUP("Aggregating Counters", INT_MAX, gen5_raw_aggregating_counters),
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};
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const static struct brw_perf_bo_layout gen5_perf_bo_layout[] =
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{
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{ -1, -1, }, /* Report ID */
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{ -1, -1, }, /* TIMESTAMP (64-bit) */
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{ -1, -1, }, /* ...second half... */
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{ 0, 0, }, /* cycles the CS unit is starved */
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{ 0, 1, }, /* cycles the CS unit is stalled */
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{ 0, 2, }, /* cycles the VF unit is starved */
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{ 0, 3, }, /* cycles the VF unit is stalled */
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{ 0, 4, }, /* cycles the VS unit is starved */
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{ 0, 5, }, /* cycles the VS unit is stalled */
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{ 0, 6, }, /* cycles the GS unit is starved */
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{ 0, 7, }, /* cycles the GS unit is stalled */
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{ 0, 8, }, /* cycles the CL unit is starved */
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{ 0, 9, }, /* cycles the CL unit is stalled */
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{ 0, 10, }, /* cycles the SF unit is starved */
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{ 0, 11, }, /* cycles the SF unit is stalled */
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{ 0, 12, }, /* cycles the WZ unit is starved */
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{ 0, 13, }, /* cycles the WZ unit is stalled */
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{ 0, 14, }, /* Z buffer read/write */
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{ 0, 15, }, /* cycles each EU was active */
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{ 0, 16, }, /* cycles each EU was suspended */
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{ 0, 17, }, /* cycles threads loaded all EUs */
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{ 0, 18, }, /* cycles filtering active */
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{ 0, 19, }, /* cycles PS threads executed */
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{ 0, 20, }, /* subspans written to RC */
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{ 0, 21, }, /* bytes read for texture reads */
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{ 0, 22, }, /* texels returned from sampler */
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{ 0, 23, }, /* polygons not culled */
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{ 0, 24, }, /* clocks MASF has valid message */
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{ 0, 25, }, /* 64b writes/reads from RC */
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{ 0, 26, }, /* reads on dataport */
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{ 0, 27, }, /* clocks MASF has valid msg not consumed by sampler */
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{ 0, 28, }, /* cycles any EU is stalled for math */
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};
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/** @} */
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/******************************************************************************/
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static void
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snapshot_aggregating_counters(struct brw_context *brw,
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drm_intel_bo *bo, uint32_t offset_in_bytes)
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{
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uint32_t report_id = offset_in_bytes == 0 ? FIRST_SNAPSHOT_REPORT_ID
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: SECOND_SNAPSHOT_REPORT_ID;
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if (brw->gen == 5) {
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/* Ironlake requires two MI_REPORT_PERF_COUNT commands to write all
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* the counters. The report ID is ignored in the second set.
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*/
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BEGIN_BATCH(6);
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OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | GEN5_MI_COUNTER_SET_0);
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OUT_RELOC(bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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offset_in_bytes);
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OUT_BATCH(report_id);
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OUT_BATCH(GEN5_MI_REPORT_PERF_COUNT | GEN5_MI_COUNTER_SET_1);
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OUT_RELOC(bo,
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I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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offset_in_bytes + 64);
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OUT_BATCH(report_id);
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ADVANCE_BATCH();
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} else {
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assert(!"Unsupported generation for performance counters.");
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}
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}
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static bool
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aggregating_counters_needed(struct brw_context *brw,
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struct gl_perf_monitor_object *m)
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{
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return m->ActiveGroups[0];
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}
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/******************************************************************************/
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/**
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* Create a new performance monitor object.
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*/
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static struct gl_perf_monitor_object *
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brw_new_perf_monitor(struct gl_context *ctx)
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{
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return calloc(1, sizeof(struct brw_perf_monitor_object));
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}
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/**
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* Delete a performance monitor object.
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*/
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static void
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brw_delete_perf_monitor(struct gl_context *ctx, struct gl_perf_monitor_object *m)
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{
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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if (monitor->bo)
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drm_intel_bo_unreference(monitor->bo);
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free(monitor);
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}
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/**
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* Driver hook for glBeginPerformanceMonitorAMD().
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*/
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static GLboolean
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brw_begin_perf_monitor(struct gl_context *ctx,
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struct gl_perf_monitor_object *m)
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{
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struct brw_context *brw = brw_context(ctx);
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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/* If the BO already exists, throw it away. It contains old results
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* that we're not interested in any more.
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*/
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if (monitor->bo)
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drm_intel_bo_unreference(monitor->bo);
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/* Create a new BO. */
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monitor->bo =
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drm_intel_bo_alloc(brw->bufmgr, "performance monitor", 4096, 64);
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drm_intel_bo_map(monitor->bo, true);
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memset((char *) monitor->bo->virtual, 0xff, 4096);
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drm_intel_bo_unmap(monitor->bo);
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/* Take a shapshot of all active counters */
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if (aggregating_counters_needed(brw, m)) {
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snapshot_aggregating_counters(brw, monitor->bo, 0);
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}
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return true;
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}
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/**
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* Driver hook for glEndPerformanceMonitorAMD().
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*/
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static void
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brw_end_perf_monitor(struct gl_context *ctx,
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struct gl_perf_monitor_object *m)
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{
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struct brw_context *brw = brw_context(ctx);
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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if (aggregating_counters_needed(brw, m)) {
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snapshot_aggregating_counters(brw, monitor->bo,
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SECOND_SNAPSHOT_OFFSET_IN_BYTES);
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}
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}
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/**
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* Reset a performance monitor, throwing away any results.
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*/
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static void
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brw_reset_perf_monitor(struct gl_context *ctx,
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struct gl_perf_monitor_object *m)
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{
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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if (monitor->bo) {
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drm_intel_bo_unreference(monitor->bo);
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monitor->bo = NULL;
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}
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if (m->Active) {
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brw_begin_perf_monitor(ctx, m);
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}
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}
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/**
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* Is a performance monitor result available?
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*/
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static GLboolean
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brw_is_perf_monitor_result_available(struct gl_context *ctx,
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struct gl_perf_monitor_object *m)
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{
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struct brw_context *brw = brw_context(ctx);
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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return !m->Active && monitor->bo &&
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!drm_intel_bo_references(brw->batch.bo, monitor->bo) &&
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!drm_intel_bo_busy(monitor->bo);
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}
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/**
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* Get the performance monitor result.
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*/
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static void
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brw_get_perf_monitor_result(struct gl_context *ctx,
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struct gl_perf_monitor_object *m,
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GLsizei data_size,
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GLuint *data,
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GLint *bytes_written)
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{
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struct brw_context *brw = brw_context(ctx);
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struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
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/* This hook should only be called when results are available. */
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assert(monitor->bo != NULL);
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drm_intel_bo_map(monitor->bo, false);
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unsigned *gpu_bo = monitor->bo->virtual;
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/* Copy data from the BO to the supplied array.
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*
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* The output data format is: <group ID, counter ID, value> for each
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* active counter. The API allows counters to appear in any order.
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*/
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GLsizei offset = 0;
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/* Look for expected report ID values to ensure data is present. */
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assert(gpu_bo[0] == FIRST_SNAPSHOT_REPORT_ID);
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assert(gpu_bo[SECOND_SNAPSHOT_OFFSET_IN_BYTES/4] == SECOND_SNAPSHOT_REPORT_ID);
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for (int i = 0; i < brw->perfmon.entries_in_bo; i++) {
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int group = brw->perfmon.bo_layout[i].group;
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int counter = brw->perfmon.bo_layout[i].counter;
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if (group < 0 || !BITSET_TEST(m->ActiveCounters[group], counter))
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continue;
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const struct gl_perf_monitor_group *group_obj =
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&ctx->PerfMonitor.Groups[group];
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const struct gl_perf_monitor_counter *c = &group_obj->Counters[counter];
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data[offset++] = group;
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data[offset++] = counter;
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uint32_t second_snapshot_index =
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SECOND_SNAPSHOT_OFFSET_IN_BYTES / sizeof(uint32_t) + i;
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/* Won't work for uint64_t values, but we don't expose any yet. */
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data[offset] = gpu_bo[second_snapshot_index] - gpu_bo[i];
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offset += _mesa_perf_monitor_counter_size(c) / sizeof(uint32_t);
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}
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drm_intel_bo_unmap(monitor->bo);
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if (bytes_written)
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*bytes_written = offset * sizeof(uint32_t);
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}
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||||
|
||||
void
|
||||
brw_init_performance_monitors(struct brw_context *brw)
|
||||
{
|
||||
struct gl_context *ctx = &brw->ctx;
|
||||
|
||||
ctx->Driver.NewPerfMonitor = brw_new_perf_monitor;
|
||||
ctx->Driver.DeletePerfMonitor = brw_delete_perf_monitor;
|
||||
ctx->Driver.BeginPerfMonitor = brw_begin_perf_monitor;
|
||||
ctx->Driver.EndPerfMonitor = brw_end_perf_monitor;
|
||||
ctx->Driver.ResetPerfMonitor = brw_reset_perf_monitor;
|
||||
ctx->Driver.IsPerfMonitorResultAvailable = brw_is_perf_monitor_result_available;
|
||||
ctx->Driver.GetPerfMonitorResult = brw_get_perf_monitor_result;
|
||||
|
||||
if (brw->gen == 5) {
|
||||
ctx->PerfMonitor.Groups = gen5_groups;
|
||||
ctx->PerfMonitor.NumGroups = ARRAY_SIZE(gen5_groups);
|
||||
brw->perfmon.bo_layout = gen5_perf_bo_layout;
|
||||
brw->perfmon.entries_in_bo = ARRAY_SIZE(gen5_perf_bo_layout);
|
||||
}
|
||||
}
|
||||
|
|
@ -160,6 +160,9 @@ intelInitExtensions(struct gl_context *ctx)
|
|||
ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
|
||||
}
|
||||
|
||||
if (brw->gen == 5)
|
||||
ctx->Extensions.AMD_performance_monitor = true;
|
||||
|
||||
if (ctx->API == API_OPENGL_CORE)
|
||||
ctx->Extensions.ARB_base_instance = true;
|
||||
if (ctx->API != API_OPENGL_CORE)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue