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intel/genxml/gfx125: Fix definition of INTERFACE_DESCRIPTOR_DATA::Thread group dispatch size

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It was using the wrong platform definition that only had 1 bit,
filtering by DG2/ACM it shows the correct definition.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28505>
This commit is contained in:
José Roberto de Souza 2024-03-27 14:08:08 -07:00 • committed by Marge Bot
parent c00c685f84
commit 0f29b780e1
1 changed files with 4 additions and 2 deletions
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6
src/intel/genxml/gen125.xml
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@ -83,9 +83,11 @@
<value name="RD" value="2" />
<value name="RTZ" value="3" />
</field>
<field name="Thread group dispatch size" start="187" end="187" type="uint">
<field name="Thread Group Dispatch Size" start="186" end="187" type="uint">
<value name="TG size 8" value="0" />
<value name="TG size 16" value="1" />
<value name="TG size 4" value="1" />
<value name="TG size 2" value="2" />
<value name="TG size 1" value="3" />
</field>
<field name="Number Of Barriers" start="188" end="190" type="uint" prefix="BARRIER_SIZE">
<value name="NONE" value="0" />