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iris/gfx12: Invalidate ISP at the end of every batch.
As requested by Ken since we're now (after 20e2c7308f)
re-emitting constants at the beginning of every batch which may lead
to some redundant constant restore overhead. No statistically
significant performance changes observed with either change.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9903>
This commit is contained in:
parent
5b9253c287
commit
0f247cc8a9
2 changed files with 19 additions and 4 deletions
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@ -541,6 +541,20 @@ finish_seqno(struct iris_batch *batch)
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static void
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iris_finish_batch(struct iris_batch *batch)
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{
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const struct gen_device_info *devinfo = &batch->screen->devinfo;
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if (devinfo->ver == 12 && batch->name == IRIS_BATCH_RENDER) {
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/* We re-emit constants at the beginning of every batch as a hardware
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* bug workaround, so invalidate indirect state pointers in order to
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* save ourselves the overhead of restoring constants redundantly when
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* the next render batch is executed.
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*/
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iris_emit_pipe_control_flush(batch, "ISP invalidate at batch end",
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PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE |
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PIPE_CONTROL_STALL_AT_SCOREBOARD |
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PIPE_CONTROL_CS_STALL);
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}
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add_aux_map_bos_to_batch(batch);
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finish_seqno(batch);
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@ -41,11 +41,12 @@ struct iris_context;
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/* The kernel assumes batchbuffers are smaller than 256kB. */
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#define MAX_BATCH_SIZE (256 * 1024)
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/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
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* or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus another
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* 24 bytes for the seqno write (using PIPE_CONTROL).
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/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END or 12
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* bytes for MI_BATCH_BUFFER_START (when chaining). Plus another 24 bytes for
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* the seqno write (using PIPE_CONTROL), and another 24 bytes for the ISP
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* invalidation pipe control.
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*/
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#define BATCH_RESERVED 36
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#define BATCH_RESERVED 60
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/* Our target batch size - flush approximately at this point. */
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#define BATCH_SZ (64 * 1024 - BATCH_RESERVED)
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