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i965/gen8: Fix antialiased line rendering with width < 1.5

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The same fix Marius implemented for gen6 (commit a9b04d8a) and
gen7 (commit 24ecf37a).

Also, we need the same code to handle special cases of line width
in gen6, gen7 and now gen8, so put that in the helper function
we use to compute the line width.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Iago Toral Quiroga 2015-06-11 08:49:46 +02:00
parent 5b61cb1236
commit 0f1fe649b7
4 changed files with 30 additions and 49 deletions
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31
src/mesa/drivers/dri/i965/brw_util.h
View file

@ -41,7 +41,7 @@ extern GLuint brw_translate_blend_factor( GLenum factor );
extern GLuint brw_translate_blend_equation( GLenum mode );
extern GLenum brw_fix_xRGB_alpha(GLenum function);
static inline float
static inline uint32_t
brw_get_line_width(struct brw_context *brw)
{
/* From the OpenGL 4.4 spec:
@ -50,9 +50,32 @@ brw_get_line_width(struct brw_context *brw)
* the supplied width to the nearest integer, then clamping it to the
* implementation-dependent maximum non-antialiased line width."
*/
return CLAMP(!brw->ctx.Multisample._Enabled && !brw->ctx.Line.SmoothFlag
? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
0.0, brw->ctx.Const.MaxLineWidth);
float line_width =
CLAMP(!brw->ctx.Multisample._Enabled && !brw->ctx.Line.SmoothFlag
? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
0.0, brw->ctx.Const.MaxLineWidth);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
/* Line width of 0 is not allowed when MSAA enabled */
if (brw->ctx.Multisample._Enabled) {
if (line_width_u3_7 == 0)
line_width_u3_7 = 1;
} else if (brw->ctx.Line.SmoothFlag && line_width < 1.5) {
/* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated. Setting a Line Width of 0.0 specifies the
* rasterization of the "thinnest" (one-pixel-wide),
* non-antialiased lines.
*
* Lines rendered with zero Line Width are rasterized using
* Grid Intersection Quantization rules as specified by
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
line_width_u3_7 = 0;
}
return line_width_u3_7;
}
#endif

22
src/mesa/drivers/dri/i965/gen6_sf_state.c
View file

@ -361,27 +361,7 @@ upload_sf_state(struct brw_context *brw)
/* _NEW_LINE */
{
float line_width = brw_get_line_width(brw);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
/* Line width of 0 is not allowed when MSAA enabled */
if (ctx->Multisample._Enabled) {
if (line_width_u3_7 == 0)
line_width_u3_7 = 1;
} else if (ctx->Line.SmoothFlag && ctx->Line.Width < 1.5) {
/* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated. Setting a Line Width of 0.0 specifies the
* rasterization of the "thinnest" (one-pixel-wide),
* non-antialiased lines.
*
* Lines rendered with zero Line Width are rasterized using
* Grid Intersection Quantization rules as specified by
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
line_width_u3_7 = 0;
}
uint32_t line_width_u3_7 = brw_get_line_width(brw);
dw3 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx->Line.SmoothFlag) {

21
src/mesa/drivers/dri/i965/gen7_sf_state.c
View file

@ -192,26 +192,7 @@ upload_sf_state(struct brw_context *brw)
/* _NEW_LINE */
{
float line_width = brw_get_line_width(brw);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
/* Line width of 0 is not allowed when MSAA enabled */
if (ctx->Multisample._Enabled) {
if (line_width_u3_7 == 0)
line_width_u3_7 = 1;
} else if (ctx->Line.SmoothFlag && ctx->Line.Width < 1.5) {
/* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated. Setting a Line Width of 0.0 specifies the
* rasterization of the "thinnest" (one-pixel-wide),
* non-antialiased lines.
*
* Lines rendered with zero Line Width are rasterized using
* Grid Intersection Quantization rules as specified by
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
line_width_u3_7 = 0;
}
uint32_t line_width_u3_7 = brw_get_line_width(brw);
dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx->Line.SmoothFlag) {

5
src/mesa/drivers/dri/i965/gen8_sf_state.c
View file

@ -154,10 +154,7 @@ upload_sf(struct brw_context *brw)
dw1 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
/* _NEW_LINE */
float line_width = brw_get_line_width(brw);
uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
if (line_width_u3_7 == 0)
line_width_u3_7 = 1;
uint32_t line_width_u3_7 = brw_get_line_width(brw);
if (brw->gen >= 9 || brw->is_cherryview) {
dw1 |= line_width_u3_7 << GEN9_SF_LINE_WIDTH_SHIFT;
} else {