From 0e96f0f8cd1ef02fcedf68f1d0afd9ce403fa0d8 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Wed, 27 Jan 2021 13:00:30 +0100 Subject: [PATCH] broadcom/compiler: prepare TMU spilling code to account for TMU pipelining MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow-up patches will implement support for TMU pipelining in the compiler, which basically means that we will be able to have more than one outstanding TMU operation. Our spilling code currently relies on properly identifying the end of a TMU sequence (since we can't emit a new TMU sequence for a spill in the middle of an existing TMU sequence), however, that code expects that only one TMU sequence may be outstanding, which won't be true once we implement pipelining. This change fixes the 'end of TMU sequence' checks to account for this in preparation for upcoming patches. Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/vir_register_allocate.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c index 3e20faf94cc..1be36ccbace 100644 --- a/src/broadcom/compiler/vir_register_allocate.c +++ b/src/broadcom/compiler/vir_register_allocate.c @@ -44,17 +44,20 @@ qinst_writes_tmu(struct qinst *inst) static bool is_end_of_tmu_sequence(struct qinst *inst, struct qblock *block) { - if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && - inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) - return true; - - if (!inst->qpu.sig.ldtmu) + if (!inst->qpu.sig.ldtmu && + !(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && + inst->qpu.alu.add.op != V3D_QPU_A_TMUWT)) { return false; + } list_for_each_entry_from(struct qinst, scan_inst, inst->link.next, &block->instructions, link) { - if (scan_inst->qpu.sig.ldtmu) + if (scan_inst->qpu.sig.ldtmu || + (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && + inst->qpu.alu.add.op == V3D_QPU_A_TMUWT)) { return false; + } + if (qinst_writes_tmu(scan_inst)) return true; }