diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c
index 516e35b4cb0..84c7616b425 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_io.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_io.c
@@ -141,12 +141,12 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s
       }
    } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
       NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, map_input, info->vs.tcs_in_out_eq);
-      NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, map_output, pdev->info.gfx_level, info->tcs.tes_inputs_read,
-                 info->tcs.tes_patch_inputs_read, info->wave_size, false, false);
+      NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, radv_map_io_driver_location, pdev->info.gfx_level,
+                 info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->wave_size, false, false);
 
       return true;
    } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-      NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, map_input);
+      NIR_PASS_V(nir, ac_nir_lower_tes_inputs_to_mem, radv_map_io_driver_location);
 
       if (info->tes.as_es) {
          NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem, map_output, pdev->info.gfx_level, info->esgs_itemsize);
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 428aad57450..17ab3cee0f6 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -1474,12 +1474,16 @@ radv_link_tcs(const struct radv_device *device, struct radv_shader_stage *tcs_st
    /* Copy TCS info into the TES info */
    merge_tess_info(&tes_stage->nir->info, &tcs_stage->nir->info);
 
-   nir_linked_io_var_info tcs2tes = nir_assign_linked_io_var_locations(tcs_stage->nir, tes_stage->nir);
+   /* Count the number of per-vertex output slots we need to reserve for the TCS and TES. */
+   const uint64_t nir_mask = tcs_stage->nir->info.outputs_written & tes_stage->nir->info.inputs_read &
+                             ~(VARYING_SLOT_TESS_LEVEL_OUTER | VARYING_SLOT_TESS_LEVEL_INNER);
+   const uint64_t io_mask = radv_gather_unlinked_io_mask(nir_mask);
+   const unsigned num_reserved_outputs = util_last_bit64(io_mask);
 
-   tcs_stage->info.tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
+   tcs_stage->info.tcs.num_linked_outputs = num_reserved_outputs;
    tcs_stage->info.outputs_linked = true;
 
-   tes_stage->info.tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
+   tes_stage->info.tes.num_linked_inputs = num_reserved_outputs;
    tes_stage->info.inputs_linked = true;
 }