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radeonsi: disable dcc for 2x MSAA surface and bpe < 4

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This fixes a series of dEQP tests on Raven platforms:
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgba4
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb5_a1
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb565
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rg8
  - dEQP-GLES3.functional.fbo.msaa.2_samples.r16f

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2019-12-13 17:38:27 +01:00 • committed by Marge Bot
parent 4202cf8bf1
commit 0e286f6cbf
1 changed files with 3 additions and 1 deletions
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4
src/gallium/drivers/radeonsi/si_texture.c
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@ -293,7 +293,9 @@ static int si_init_surface(struct si_screen *sscreen,
/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
if (sscreen->info.chip_class == GFX9 &&
ptex->nr_storage_samples >= 4)
(ptex->nr_storage_samples >= 4 ||
(sscreen->info.family == CHIP_RAVEN &&
ptex->nr_storage_samples >= 2 && bpe < 4)))
flags |= RADEON_SURF_DISABLE_DCC;
/* TODO: GFX10: DCC causes corruption with MSAA. */