fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-26 06:20:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/state: Emit pipeline select when changing pipelines

Browse source 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2015-04-22 11:43:50 -07:00
parent 013031b229
commit 0e0e23ef53
4 changed files with 36 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1148,6 +1148,8 @@ struct brw_context
struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
} state;
enum brw_pipeline last_pipeline;
struct brw_cache cache;
/** IDs for meta stencil blit shader programs. */

23
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -854,6 +854,22 @@ const struct brw_tracked_state brw_line_stipple = {
};
void
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
/* Select the pipeline */
BEGIN_BATCH(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 |
(brw->gen >= 9 ? (3 << 8) : 0) |
(pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
ADVANCE_BATCH();
}
/***********************************************************************
* Misc invariant state packets
*/
@ -863,12 +879,7 @@ brw_upload_invariant_state(struct brw_context *brw)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
/* Select the 3D pipeline (as opposed to media) */
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
BEGIN_BATCH(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0));
ADVANCE_BATCH();
brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
if (brw->gen < 6) {
/* Disable depth offset clamping. */

12
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -185,6 +185,18 @@ void brw_upload_compute_state(struct brw_context *brw);
void brw_compute_state_finished(struct brw_context *brw);
void brw_init_state(struct brw_context *brw);
void brw_destroy_state(struct brw_context *brw);
void brw_emit_select_pipeline(struct brw_context *brw,
enum brw_pipeline pipeline);
static inline void
brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
if (unlikely(brw->last_pipeline != pipeline)) {
assert(pipeline < BRW_NUM_PIPELINES);
brw_emit_select_pipeline(brw, pipeline);
brw->last_pipeline = pipeline;
}
}
/***********************************************************************
* brw_state_cache.c

5
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -406,6 +406,9 @@ void brw_init_state( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
/* Force the first brw_select_pipeline to emit pipeline select */
brw->last_pipeline = BRW_NUM_PIPELINES;
STATIC_ASSERT(ARRAY_SIZE(gen4_atoms) <= ARRAY_SIZE(brw->render_atoms));
STATIC_ASSERT(ARRAY_SIZE(gen6_atoms) <= ARRAY_SIZE(brw->render_atoms));
STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms) <=
@ -656,6 +659,8 @@ brw_upload_pipeline_state(struct brw_context *brw,
static int dirty_count = 0;
struct brw_state_flags state = brw->state.pipelines[pipeline];
brw_select_pipeline(brw, pipeline);
if (0) {
/* Always re-emit all state. */
brw->NewGLState = ~0;