From 0e076355cc7f5953bc0e75120af6be12890b2380 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 30 Sep 2020 15:41:00 +0200 Subject: [PATCH] aco: implement missing nir_op_unpack_half_2x16_split_{x,y}_flush_to_zero MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPIRV->NIR emits nir_op_unpack_half_2x16_flush_to_zero instead of nir_op_unpack_half_2x16 if the shader enables denorm flush to zero for 16-bit floating point. This doesn't fix anything known and CTS doesn't have tests. Fixes: 56d9bcdded8 ("radv: enable more float_controls features") Signed-off-by: Samuel Pitoiset Reviewed-by: Daniel Schürmann Part-of: (cherry picked from commit b9ca4923d6c33af76dd25548bc8ec975d0bfe96c) --- .pick_status.json | 2 +- src/amd/compiler/aco_instruction_selection.cpp | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index e02d0a747fd..44dbf34ddd6 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -5125,7 +5125,7 @@ "description": "aco: implement missing nir_op_unpack_half_2x16_split_{x,y}_flush_to_zero", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "56d9bcdded8f3eb7bd45262ce013ef1809d8edb1" }, diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 0f151cb481e..f98499fcc3b 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2857,8 +2857,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } break; } + case nir_op_unpack_half_2x16_split_x_flush_to_zero: case nir_op_unpack_half_2x16_split_x: { if (dst.regClass() == v1) { + assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_x_flush_to_zero)); bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0])); } else { fprintf(stderr, "Unimplemented NIR instr bit size: "); @@ -2867,8 +2869,10 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } break; } + case nir_op_unpack_half_2x16_split_y_flush_to_zero: case nir_op_unpack_half_2x16_split_y: { if (dst.regClass() == v1) { + assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_y_flush_to_zero)); /* TODO: use SDWA here */ bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));