radv, radeonsi: don't use D16 for f2f16_rtz

D16 rounds towards zero for fp32 -> fp16, but for fixed point it rounds to
nearest even in fp16. MIMG without D16 also rounds to nearest even, but in fp32.
This means D16 and f2f16_rtz(tex@32) can produce different results.

Sadly this also means we can never use d16 if fp16 rounding isn't undefined.

Cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
(cherry picked from commit 3a35522c8a)

.pick_status.json

@@ -34,7 +34,7 @@
         "description": "radv, radeonsi: don't use D16 for f2f16_rtz",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null

src/amd/vulkan/radv_pipeline.c

@@ -701,7 +701,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_pipeline_key
          },
       };
       struct nir_fold_16bit_tex_image_options fold_16bit_options = {
-         .rounding_mode = nir_rounding_mode_rtz,
+         .rounding_mode = nir_rounding_mode_undef,
          .fold_tex_dest_types = nir_type_float,
          .fold_image_dest_types = nir_type_float,
          .fold_image_store_data = true,

src/gallium/drivers/radeonsi/si_shader_nir.c

@@ -208,7 +208,7 @@ static void si_late_optimize_16bit_samplers(struct si_screen *sscreen, nir_shade
       },
    };
    struct nir_fold_16bit_tex_image_options fold_16bit_options = {
-      .rounding_mode = nir_rounding_mode_rtz,
+      .rounding_mode = nir_rounding_mode_undef,
       .fold_tex_dest_types = nir_type_float,
       .fold_image_dest_types = nir_type_float,
       .fold_image_store_data = true,