diff --git a/src/gallium/drivers/r300/ci/r300-rv515-fails.txt b/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
index d92062c9c3e..f79d4b51707 100644
--- a/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
+++ b/src/gallium/drivers/r300/ci/r300-rv515-fails.txt
@@ -41,8 +41,6 @@ dEQP-GLES2.functional.rasterization.primitives.lines_wide,Fail
 dEQP-GLES2.functional.rasterization.primitives.line_strip_wide,Fail,Fail
 dEQP-GLES2.functional.rasterization.primitives.line_loop_wide,Fail
 
-dEQP-GLES2.functional.shaders.discard.dynamic_loop_always,Fail
-
 dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_write_dynamic_loop_read_fragment,Fail
 
 dEQP-GLES2.functional.shaders.random.texture.fragment.141,Fail
diff --git a/src/gallium/drivers/r300/compiler/r500_fragprog_emit.c b/src/gallium/drivers/r300/compiler/r500_fragprog_emit.c
index f308b84f1c5..7d5bcbeae57 100644
--- a/src/gallium/drivers/r300/compiler/r500_fragprog_emit.c
+++ b/src/gallium/drivers/r300/compiler/r500_fragprog_emit.c
@@ -460,6 +460,7 @@ static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst
 		s->Code->int_constant_count = 1;
 	}
 	s->Code->inst[newip].inst0 = R500_INST_TYPE_FC | R500_INST_ALU_WAIT;
+	s->Code->inst[newip].inst0 |= (inst->U.I.TexSemWait << R500_INST_TEX_SEM_WAIT_SHIFT);
 
 	switch(inst->U.I.Opcode){
 	struct branch_info * branch;
diff --git a/src/gallium/drivers/r300/compiler/radeon_pair_schedule.c b/src/gallium/drivers/r300/compiler/radeon_pair_schedule.c
index e30d6bec014..73518c34cb7 100644
--- a/src/gallium/drivers/r300/compiler/radeon_pair_schedule.c
+++ b/src/gallium/drivers/r300/compiler/radeon_pair_schedule.c
@@ -153,6 +153,7 @@ struct schedule_state {
 	void (*CalcScore)(struct schedule_instruction *);
 	long max_tex_group;
 	unsigned PrevBlockHasTex:1;
+	unsigned PrevBlockHasKil:1;
 	unsigned TEXCount;
 	unsigned Opt:1;
 };
@@ -1102,6 +1103,7 @@ static void emit_instruction(
 	for (tex_ptr = s->ReadyTEX; tex_ptr; tex_ptr = tex_ptr->NextReady) {
 		if (tex_ptr->Instruction->U.I.Opcode == RC_OPCODE_KIL) {
 			emit_all_tex(s, before);
+			s->PrevBlockHasKil = 1;
 			return;
 		}
 		tex_count++;
@@ -1335,6 +1337,16 @@ void rc_pair_schedule(struct radeon_compiler *cc, void *user)
 		struct rc_instruction * first;
 
 		if (is_controlflow(inst)) {
+			/* The TexSemWait flag is already properly set for ALU
+			 * instructions using the results of normal TEX lookup,
+			 * however it was found empirically that TEXKIL also needs
+			 * synchronization with the control flow. This might not be optimal,
+			 * however the docs don't offer any guidance in this matter.
+			 */
+			if (s.PrevBlockHasKil) {
+				inst->U.I.TexSemWait = 1;
+				s.PrevBlockHasKil = 0;
+			}
 			inst = inst->Next;
 			continue;
 		}