From 0de929e73e9d76fbad021fa7339e76d5eeae997d Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 26 Jun 2023 17:03:08 +0200 Subject: [PATCH] etnaviv: Emit MRT states We do not need to emit states for render targets 1..7 as the GPU only processes up to VIVS_PS_CONTROL_RT_COUNT(..) ones. Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach Part-of: --- src/gallium/drivers/etnaviv/etnaviv_emit.c | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index 4e9c358d897..4d6079735c5 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -540,6 +540,37 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_SHADER))) { /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS); } + + if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { + if (screen->specs.num_rts == 4) { + for (int i = 1; i < ctx->framebuffer.num_rt; i++) { + const uint8_t rt = i - 1; + /*01500*/ EMIT_STATE_RELOC(PE_RT_ADDR_4_PIPE(rt, 0), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][0]); + /*01520*/ EMIT_STATE_RELOC(PE_RT_ADDR_4_PIPE(rt, 1), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][1]); + /*01580*/ EMIT_STATE(PE_RT_CONFIG_4(rt), ctx->framebuffer.PE_RT_CONFIG[rt]); + } + } else if (screen->specs.num_rts == 8) { + for (int i = 1; i < ctx->framebuffer.num_rt; i++) { + const uint8_t rt = i - 1; + /*14800*/ EMIT_STATE_RELOC(PE_RT_ADDR_8_PIPE(rt, 0), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][0]); + /*14800*/ EMIT_STATE_RELOC(PE_RT_ADDR_8_PIPE(rt, 1), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][1]); + /*14900*/ EMIT_STATE(PE_RT_CONFIG_8(rt), ctx->framebuffer.PE_RT_CONFIG[rt]); + } + } + } + + if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) { + for (int i = 1; i < ctx->framebuffer.num_rt; i++) { + const uint8_t rt = i - 1; + /* Index 0 is not used by the binary blob. */ + EMIT_STATE(TS_RT_CONFIG(i), ctx->framebuffer.RT_TS_MEM_CONFIG[rt]); + EMIT_STATE(TS_RT_CLEAR_VALUE(i), ctx->framebuffer.RT_TS_COLOR_CLEAR_VALUE[rt]); + EMIT_STATE(TS_RT_CLEAR_VALUE2(i), ctx->framebuffer.RT_TS_COLOR_CLEAR_VALUE_EXT[rt]); + EMIT_STATE_RELOC(TS_RT_STATUS_BASE(i), &ctx->framebuffer.RT_TS_COLOR_STATUS_BASE[rt]); + EMIT_STATE_RELOC(TS_RT_SURFACE_BASE(i), &ctx->framebuffer.RT_TS_COLOR_SURFACE_BASE[rt]); + } + } + etna_coalesce_end(stream, &coalesce); /* end only EMIT_STATE */