diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 16898357537..68d9ed3abda 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1003,6 +1003,15 @@ isl_surf_choose_tiling(const struct isl_device *dev, CHOOSE(ISL_TILING_LINEAR); } + /* For sparse images, prefer the formats that use the standard block + * shapes. + */ + if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) { + CHOOSE(ISL_TILING_64); + CHOOSE(ISL_TILING_ICL_Ys); + CHOOSE(ISL_TILING_SKL_Ys); + } + /* Choose suggested 4K tilings first, then 64K tilings: * * Then following quotes can be found in the SKL PRMs, @@ -2454,6 +2463,14 @@ isl_calc_size(const struct isl_device *dev, row_pitch_B; } + /* If for some reason we can't support the appropriate tiling format and + * end up falling to linear or some other format, make sure the image size + * and alignment are aligned to the expected block size so we can at least + * do opaque binds. + */ + if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) + size_B = isl_align(size_B, 64 * 1024); + if (ISL_GFX_VER(dev) < 9) { /* From the Broadwell PRM Vol 5, Surface Layout: * @@ -2563,6 +2580,14 @@ isl_calc_base_alignment(const struct isl_device *dev, } } + /* If for some reason we can't support the appropriate tiling format and + * end up falling to linear or some other format, make sure the image size + * and alignment are aligned to the expected block size so we can at least + * do opaque binds. + */ + if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) + base_alignment_B = MAX(base_alignment_B, 64 * 1024); + return base_alignment_B; } diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index e83c082e05c..beb5d33a70a 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1128,6 +1128,7 @@ typedef uint64_t isl_surf_usage_flags_t; #define ISL_SURF_USAGE_VIDEO_DECODE_BIT (1u << 17) #define ISL_SURF_USAGE_STREAM_OUT_BIT (1u << 18) #define ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT (1u << 19) +#define ISL_SURF_USAGE_SPARSE_BIT (1u << 20) /** @} */ /**