From 0dc16965a99e2583202a2be4ef9fb7947b6828b2 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 7 Dec 2018 14:15:03 -0800 Subject: [PATCH] intel/fs: Fix repclear assembly for XeHP+ regioning restrictions. The regioning mode used here is no longer supported by the floating-point pipeline. We could run the regioning lowering pass in order to fix it with some extra copies, but it's more efficient to change the instruction to use integer types. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 96ce9ec8885..9cd9a0cd926 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3412,12 +3412,12 @@ fs_visitor::emit_repclear_shader() fs_reg(UNIFORM, 0, BRW_REGISTER_TYPE_F)); } else { struct brw_reg reg = - brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_F, + brw_reg(BRW_GENERAL_REGISTER_FILE, 2, 3, 0, 0, BRW_REGISTER_TYPE_UD, BRW_VERTICAL_STRIDE_8, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_4, BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); mov = bld.exec_all().group(4, 0) - .MOV(vec4(brw_message_reg(color_mrf)), fs_reg(reg)); + .MOV(brw_uvec_mrf(4, color_mrf, 0), fs_reg(reg)); } fs_inst *write = NULL;