diff --git a/src/amd/compiler/aco_interface.h b/src/amd/compiler/aco_interface.h
index f1b6b91c36a..9963f8eeb8c 100644
--- a/src/amd/compiler/aco_interface.h
+++ b/src/amd/compiler/aco_interface.h
@@ -37,6 +37,7 @@ extern "C" {
 struct ac_shader_config;
 struct aco_shader_info;
 struct aco_vs_prolog_key;
+struct aco_ps_epilog_key;
 
 struct aco_compiler_statistic_info {
    char name[32];
diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index 92eab124b4c..38c98dff27f 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -60,6 +60,15 @@ struct aco_vs_prolog_key {
    gl_shader_stage next_stage;
 };
 
+struct aco_ps_epilog_key {
+   uint32_t spi_shader_col_format;
+
+   /* Bitmasks, each bit represents one of the 8 MRTs. */
+   uint8_t color_is_int8;
+   uint8_t color_is_int10;
+   uint8_t enable_mrt_output_nan_fixup;
+};
+
 struct aco_vp_output_info {
    uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
    uint8_t clip_dist_mask;
diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h
index 0f6b64a2b8d..239986963c8 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -123,6 +123,16 @@ radv_aco_convert_vs_prolog_key(struct aco_vs_prolog_key *aco_info,
    ASSIGN_FIELD(next_stage);
 }
 
+static inline void
+radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_key *aco_info,
+			       const struct radv_ps_epilog_key *radv)
+{
+   ASSIGN_FIELD(spi_shader_col_format);
+   ASSIGN_FIELD(color_is_int8);
+   ASSIGN_FIELD(color_is_int10);
+   ASSIGN_FIELD(enable_mrt_output_nan_fixup);
+}
+
 static inline void
 radv_aco_convert_pipe_key(struct aco_stage_input *aco_info,
                           const struct radv_pipeline_key *radv)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index e8a693129bc..96ff3f23d20 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -410,6 +410,17 @@ struct radv_vs_prolog_key {
    gl_shader_stage next_stage;
 };
 
+struct radv_ps_epilog_key {
+   uint32_t spi_shader_col_format;
+
+   /* Bitmasks, each bit represents one of the 8 MRTs. */
+   uint8_t color_is_int8;
+   uint8_t color_is_int10;
+   uint8_t enable_mrt_output_nan_fixup;
+
+   bool wave32;
+};
+
 enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
 
 struct radv_shader_binary {