radeonsi: declare prolog LINEAR_SAMPLE/CENTER VGPRs only if used

Small PS have their VGPR usage equal to the number of input VGPRs,
and this reduces it.

4 input VGPRs removed in most cases.
This commit is contained in:
Marek Olšák 2026-04-25 17:26:46 -04:00
parent a5edf2ef48
commit 0d7ae9ab73
4 changed files with 19 additions and 4 deletions

View file

@ -1746,6 +1746,12 @@ static void si_get_ps_prolog_key(struct si_shader *shader, union si_shader_part_
key->ps_prolog.states.force_samplemask_to_helper_invocation);
key->ps_prolog.uses_persp_centroid =
G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr); /* addr because the PS prolog may use it */
/* The PS prolog can change one to the other, so we need both or neither to be set. */
assert(G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr) ==
G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
key->ps_prolog.uses_linear_sample_and_center =
G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr) || /* addr because the PS prolog may use it */
G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr);
key->ps_prolog.uses_linear_centroid =
G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr); /* addr because the PS prolog may use it */
key->ps_prolog.reserve_line_stipple_tex_ena =

View file

@ -565,6 +565,7 @@ union si_shader_part_key {
unsigned colors_read : 8; /* color input components read */
unsigned num_interp_inputs : 5; /* BCOLOR is at this location */
unsigned uses_persp_centroid : 1;
unsigned uses_linear_sample_and_center : 1;
unsigned uses_linear_centroid : 1;
unsigned reserve_line_stipple_tex_ena : 1; /* only reserve the VGPR, don't use it */
unsigned fragcoord_usage_mask : 4;

View file

@ -678,8 +678,11 @@ void si_get_ps_prolog_args(struct si_shader_args *args,
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.persp_centroid);
/* skip PERSP_PULL_MODEL */
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.linear_sample);
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.linear_center);
if (key->ps_prolog.uses_linear_sample_and_center) {
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.linear_sample);
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.linear_center);
}
if (key->ps_prolog.uses_linear_centroid)
ac_add_arg(&args->ac, AC_ARG_VGPR, 2, AC_ARG_VALUE, &args->ac.linear_centroid);

View file

@ -612,8 +612,6 @@ unsigned si_get_spi_ps_input_addr_for_prolog(struct si_shader_selector *sel)
{
unsigned spi_ps_input_addr = S_0286D0_PERSP_SAMPLE_ENA(1) |
S_0286D0_PERSP_CENTER_ENA(1) |
S_0286D0_LINEAR_SAMPLE_ENA(1) |
S_0286D0_LINEAR_CENTER_ENA(1) |
S_0286D0_FRONT_FACE_ENA(1) |
S_0286D0_POS_FIXED_PT_ENA(1);
@ -623,6 +621,13 @@ unsigned si_get_spi_ps_input_addr_for_prolog(struct si_shader_selector *sel)
if (sel->info.uses_sysval_persp_centroid)
spi_ps_input_addr |= S_0286D0_PERSP_CENTROID_ENA(1);
/* The PS prolog can change one to the other, so we need both. */
if (sel->info.uses_sysval_linear_sample ||
sel->info.uses_sysval_linear_center) {
spi_ps_input_addr |= S_0286D0_LINEAR_SAMPLE_ENA(1) |
S_0286D0_LINEAR_CENTER_ENA(1);
}
if (sel->info.uses_sysval_linear_centroid)
spi_ps_input_addr |= S_0286D0_LINEAR_CENTROID_ENA(1);