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brw: drop indirection on compiler options

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I see no point, we allocate for every shader stage anyway. This is a bit
simpler.

I'm not a fan of the brw_compiler singleton at all but torching that is not on
today's agenda. Flattening it a little bit very much is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37447>
This commit is contained in:
Alyssa Rosenzweig 2025-09-17 11:20:50 -04:00 • committed by Marge Bot
parent 2c161cc35d
commit 0d7083d5bc
12 changed files with 16 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/gallium/drivers/iris/iris_program.c
View file

@ -4002,10 +4002,10 @@ iris_get_compiler_options(struct pipe_screen *pscreen,
struct iris_screen *screen = (struct iris_screen *) pscreen;
#ifdef INTEL_USE_ELK
return screen->brw ? screen->brw->nir_options[stage]
return screen->brw ? &screen->brw->nir_options[stage]
: screen->elk->nir_options[stage];
#else
return screen->brw->nir_options[stage];
return &screen->brw->nir_options[stage];
#endif
}

2
src/gallium/drivers/iris/iris_program_cache.c
View file

@ -377,7 +377,7 @@ iris_ensure_indirect_generation_shader(struct iris_batch *batch)
#ifdef INTEL_USE_ELK
screen->elk ? screen->elk->nir_options[MESA_SHADER_COMPUTE] :
#endif
screen->brw->nir_options[MESA_SHADER_COMPUTE];
&screen->brw->nir_options[MESA_SHADER_COMPUTE];
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT,
nir_options,

2
src/intel/blorp/blorp_brw.c
View file

@ -14,7 +14,7 @@ blorp_nir_options_brw(struct blorp_context *blorp,
mesa_shader_stage stage)
{
const struct brw_compiler *compiler = blorp->compiler->brw;
return compiler->nir_options[stage];
return &compiler->nir_options[stage];
}
static struct blorp_program

4
src/intel/compiler/brw_compiler.c
View file

@ -164,7 +164,7 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
struct nir_shader_compiler_options *nir_options =
rzalloc(compiler, struct nir_shader_compiler_options);
&compiler->nir_options[i];
*nir_options = brw_scalar_nir_options;
int64_options |= nir_lower_usub_sat64;
@ -201,8 +201,6 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
if (devinfo->ver < 12)
nir_options->divergence_analysis_options |=
nir_divergence_single_prim_per_subgroup;
compiler->nir_options[i] = nir_options;
}
/* Build a list of storage format compatible in component bit size &

4
src/intel/compiler/brw_compiler.h
View file

@ -35,6 +35,7 @@
#include "util/u_printf.h"
#include "brw_isa_info.h"
#include "intel_shader_enums.h"
#include "nir_shader_compiler_options.h"
#ifdef __cplusplus
extern "C" {
@ -46,7 +47,6 @@ struct nir_def;
struct nir_shader;
struct shader_info;
struct nir_shader_compiler_options;
typedef struct nir_builder nir_builder;
typedef struct nir_def nir_def;
typedef struct nir_shader nir_shader;
@ -82,7 +82,7 @@ struct brw_compiler {
void (*shader_perf_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);
bool use_tcs_multi_patch;
struct nir_shader_compiler_options *nir_options[MESA_ALL_SHADER_STAGES];
struct nir_shader_compiler_options nir_options[MESA_ALL_SHADER_STAGES];
/**
* Apply workarounds for SIN and COS output range problems.

2
src/intel/compiler/brw_nir.c
View file

@ -2698,7 +2698,7 @@ brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compile
assert(key->input_vertices > 0);
const nir_shader_compiler_options *options =
compiler->nir_options[MESA_SHADER_TESS_CTRL];
&compiler->nir_options[MESA_SHADER_TESS_CTRL];
uint64_t inputs_read = key->outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);

4
src/intel/compiler/brw_nir_lower_shader_calls.c
View file

@ -325,7 +325,7 @@ brw_nir_create_trivial_return_shader(const struct brw_compiler *compiler,
void *mem_ctx)
{
const nir_shader_compiler_options *nir_options =
compiler->nir_options[MESA_SHADER_CALLABLE];
&compiler->nir_options[MESA_SHADER_CALLABLE];
nir_builder _b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE,
nir_options,
@ -365,7 +365,7 @@ brw_nir_create_null_ahs_shader(const struct brw_compiler *compiler,
void *mem_ctx)
{
const nir_shader_compiler_options *nir_options =
compiler->nir_options[MESA_SHADER_CALLABLE];
&compiler->nir_options[MESA_SHADER_CALLABLE];
nir_builder _b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE,
nir_options,

2
src/intel/compiler/brw_nir_rt.c
View file

@ -413,7 +413,7 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
{
const struct intel_device_info *devinfo = compiler->devinfo;
const nir_shader_compiler_options *nir_options =
compiler->nir_options[MESA_SHADER_COMPUTE];
&compiler->nir_options[MESA_SHADER_COMPUTE];
STATIC_ASSERT(sizeof(struct brw_rt_raygen_trampoline_params) == 32);

2
src/intel/vulkan/anv_astc_emu.c
View file

@ -197,7 +197,7 @@ astc_emu_init_flush_denorm_pipeline_locked(struct anv_device *device)
if (astc_emu->pipeline == VK_NULL_HANDLE) {
const struct nir_shader_compiler_options *options =
device->physical->compiler->nir_options[MESA_SHADER_COMPUTE];
&device->physical->compiler->nir_options[MESA_SHADER_COMPUTE];
nir_builder b = nir_builder_init_simple_shader(
MESA_SHADER_COMPUTE, options, "astc_emu_flush_denorm");
astc_emu_init_flush_denorm_shader(&b);

2
src/intel/vulkan/anv_internal_kernels.c
View file

@ -58,7 +58,7 @@ compile_shader(struct anv_device *device,
uint32_t sends_count_expectation)
{
const nir_shader_compiler_options *nir_options =
device->physical->compiler->nir_options[stage];
&device->physical->compiler->nir_options[stage];
nir_builder b = nir_builder_init_simple_shader(stage, nir_options,
"%s", name);

2
src/intel/vulkan/anv_pipeline_cache.c
View file

@ -525,7 +525,7 @@ void
anv_load_fp64_shader(struct anv_device *device)
{
const nir_shader_compiler_options *nir_options =
device->physical->compiler->nir_options[MESA_SHADER_VERTEX];
&device->physical->compiler->nir_options[MESA_SHADER_VERTEX];
const char* shader_name = "float64_spv_lib";
struct mesa_sha1 sha1_ctx;

4
src/intel/vulkan/anv_shader_compile.c
View file

@ -147,7 +147,7 @@ anv_shader_get_nir_options(struct vk_physical_device *device,
container_of(device, struct anv_physical_device, vk);
const struct brw_compiler *compiler = pdevice->compiler;
return compiler->nir_options[stage];
return &compiler->nir_options[stage];
}
static struct spirv_to_nir_options
@ -1563,7 +1563,7 @@ anv_shaders_post_lower_gfx(struct anv_device *device,
struct shader_info *cur_info = &shader_data->info->nir->info;
if (prev_stage && compiler->nir_options[info->stage]->unify_interfaces) {
if (prev_stage && compiler->nir_options[info->stage].unify_interfaces) {
struct shader_info *prev_info = &prev_stage->nir->info;
prev_info->outputs_written |= cur_info->inputs_read &