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radeonsi: rework RB+ for Stoney

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This fixes it.

States which also need to be taken into account:
- SPI color formats - each down-conversion format supports only a limited set
  of SPI formats
- whether MSAA resolving and logic op are enabled

These need special handling:
- blending
- disabled channels

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-01-17 21:13:16 +01:00
parent 066d76c2f4
commit 0d68b91220
4 changed files with 228 additions and 109 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -261,8 +261,6 @@ struct r600_surface {
unsigned spi_shader_col_format_alpha; /* SI+, alpha-to-coverage */
unsigned spi_shader_col_format_blend; /* SI+, blending without alpha. */
unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
unsigned sx_ps_downconvert; /* Stoney only */
unsigned sx_blend_opt_epsilon; /* Stoney only */
struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */

6
src/gallium/drivers/radeon/r600_texture.c
View file

@ -1388,7 +1388,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
return;
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_surface *surf;
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
@ -1399,7 +1398,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
if (!(*buffers & clear_bit))
continue;
surf = (struct r600_surface *)fb->cbufs[i];
tex = (struct r600_texture *)fb->cbufs[i]->texture;
/* 128-bit formats are unusupported */
@ -1446,8 +1444,8 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
if (clear_words_needed)
tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
} else {
/* RB+ doesn't work with CMASK fast clear. */
if (surf->sx_ps_downconvert)
/* Stoney/RB+ doesn't work with CMASK fast clear. */
if (rctx->family == CHIP_STONEY)
continue;
/* ensure CMASK is enabled */

326
src/gallium/drivers/radeonsi/si_state.c
View file

@ -272,6 +272,143 @@ static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *a
cb_target_mask = 0;
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
/* STONEY-specific register settings. */
if (sctx->b.family == CHIP_STONEY) {
unsigned spi_shader_col_format =
sctx->ps_shader.cso ?
sctx->ps_shader.current->key.ps.spi_shader_col_format : 0;
unsigned sx_ps_downconvert = 0;
unsigned sx_blend_opt_epsilon = 0;
unsigned sx_blend_opt_control = 0;
for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
struct r600_surface *surf =
(struct r600_surface*)sctx->framebuffer.state.cbufs[i];
unsigned format, swap, spi_format, colormask;
bool has_alpha, has_rgb;
if (!surf)
continue;
format = G_028C70_FORMAT(surf->cb_color_info);
swap = G_028C70_COMP_SWAP(surf->cb_color_info);
spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
colormask = (cb_target_mask >> (i * 4)) & 0xf;
/* Set if RGB and A are present. */
has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
if (format == V_028C70_COLOR_8 ||
format == V_028C70_COLOR_16 ||
format == V_028C70_COLOR_32)
has_rgb = !has_alpha;
else
has_rgb = true;
/* Check the colormask and export format. */
if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
has_rgb = false;
if (!(colormask & PIPE_MASK_A))
has_alpha = false;
if (spi_format == V_028714_SPI_SHADER_ZERO) {
has_rgb = false;
has_alpha = false;
}
/* Disable value checking for disabled channels. */
if (!has_rgb)
sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
if (!has_alpha)
sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
/* Enable down-conversion for 32bpp and smaller formats. */
switch (format) {
case V_028C70_COLOR_8:
case V_028C70_COLOR_8_8:
case V_028C70_COLOR_8_8_8_8:
/* For 1 and 2-channel formats, use the superset thereof. */
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_5_6_5:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_1_5_5_5:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_4_4_4_4:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_32:
if (swap == V_0280A0_SWAP_STD &&
spi_format == V_028714_SPI_SHADER_32_R)
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
else if (swap == V_0280A0_SWAP_ALT_REV &&
spi_format == V_028714_SPI_SHADER_32_AR)
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
break;
case V_028C70_COLOR_16:
case V_028C70_COLOR_16_16:
/* For 1-channel formats, use the superset thereof. */
if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
if (swap == V_0280A0_SWAP_STD ||
swap == V_0280A0_SWAP_STD_REV)
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
else
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
}
break;
case V_028C70_COLOR_10_11_11:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
}
break;
case V_028C70_COLOR_2_10_10_10:
if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
}
break;
}
}
if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
sx_ps_downconvert = 0;
sx_blend_opt_epsilon = 0;
sx_blend_opt_control = 0;
}
radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
}
}
/*
@ -391,6 +528,36 @@ static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
}
}
/**
* Get rid of DST in the blend factors by commuting the operands:
* func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
*/
static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
unsigned *dst_factor, unsigned expected_dst,
unsigned replacement_src)
{
if (*src_factor == expected_dst &&
*dst_factor == PIPE_BLENDFACTOR_ZERO) {
*src_factor = PIPE_BLENDFACTOR_ZERO;
*dst_factor = replacement_src;
/* Commuting the operands requires reversing subtractions. */
if (*func == PIPE_BLEND_SUBTRACT)
*func = PIPE_BLEND_REVERSE_SUBTRACT;
else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
*func = PIPE_BLEND_SUBTRACT;
}
}
static bool si_blend_factor_uses_dst(unsigned factor)
{
return factor == PIPE_BLENDFACTOR_DST_COLOR ||
factor == PIPE_BLENDFACTOR_DST_ALPHA ||
factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
}
static void *si_create_blend_state_mode(struct pipe_context *ctx,
const struct pipe_blend_state *state,
unsigned mode)
@ -398,7 +565,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
struct si_context *sctx = (struct si_context*)ctx;
struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
struct si_pm4_state *pm4 = &blend->pm4;
uint32_t sx_mrt_blend_opt[8] = {0};
uint32_t color_control = 0;
if (!blend)
@ -436,12 +603,17 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
unsigned srcA = state->rt[j].alpha_src_factor;
unsigned dstA = state->rt[j].alpha_dst_factor;
unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
unsigned blend_cntl = 0;
sx_mrt_blend_opt[i] =
S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
if (!state->rt[j].colormask)
continue;
/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
/* cb_render_state will disable unused ones */
blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
if (!state->rt[j].blend_enable) {
@ -449,6 +621,50 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
continue;
}
/* Blending optimizations for Stoney.
* These transformations don't change the behavior.
*
* First, get rid of DST in the blend factors:
* func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
*/
si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
PIPE_BLENDFACTOR_DST_COLOR,
PIPE_BLENDFACTOR_SRC_COLOR);
si_blend_remove_dst(&eqA, &srcA, &dstA,
PIPE_BLENDFACTOR_DST_COLOR,
PIPE_BLENDFACTOR_SRC_COLOR);
si_blend_remove_dst(&eqA, &srcA, &dstA,
PIPE_BLENDFACTOR_DST_ALPHA,
PIPE_BLENDFACTOR_SRC_ALPHA);
/* Look up the ideal settings from tables. */
srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
srcA_opt = si_translate_blend_opt_factor(srcA, true);
dstA_opt = si_translate_blend_opt_factor(dstA, true);
/* Handle interdependencies. */
if (si_blend_factor_uses_dst(srcRGB))
dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
if (si_blend_factor_uses_dst(srcA))
dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
(dstRGB == PIPE_BLENDFACTOR_ZERO ||
dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
/* Set the final value. */
sx_mrt_blend_opt[i] =
S_028760_COLOR_SRC_OPT(srcRGB_opt) |
S_028760_COLOR_DST_OPT(dstRGB_opt) |
S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
S_028760_ALPHA_SRC_OPT(srcA_opt) |
S_028760_ALPHA_DST_OPT(dstA_opt) |
S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
/* Set blend state. */
blend_cntl |= S_028780_ENABLE(1);
blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
@ -481,41 +697,13 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
}
if (sctx->b.family == CHIP_STONEY) {
uint32_t sx_blend_opt_control = 0;
for (int i = 0; i < 8; i++) {
const int j = state->independent_blend_enable ? i : 0;
/* TODO: We can also set this if the surface doesn't contain RGB. */
if (!state->rt[j].blend_enable ||
!(state->rt[j].colormask & (PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B)))
sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (4 * i);
/* TODO: We can also set this if the surface doesn't contain alpha. */
if (!state->rt[j].blend_enable ||
!(state->rt[j].colormask & PIPE_MASK_A))
sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (4 * i);
if (!state->rt[j].blend_enable) {
si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED));
continue;
}
for (int i = 0; i < 8; i++)
si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
S_028760_COLOR_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_src_factor, false)) |
S_028760_COLOR_DST_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_dst_factor, false)) |
S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(state->rt[j].rgb_func)) |
S_028760_ALPHA_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_src_factor, true)) |
S_028760_ALPHA_DST_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_dst_factor, true)) |
S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(state->rt[j].alpha_func)));
}
sx_mrt_blend_opt[i]);
si_pm4_set_reg(pm4, R_02875C_SX_BLEND_OPT_CONTROL, sx_blend_opt_control);
/* RB+ doesn't work with dual source blending */
if (blend->dual_src_blend)
/* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
if (blend->dual_src_blend || state->logicop_enable ||
mode == V_028808_CB_RESOLVE)
color_control |= S_028808_DISABLE_DUAL_QUAD(1);
}
@ -2172,61 +2360,6 @@ static void si_initialize_color_surface(struct si_context *sctx,
/* Determine pixel shader export format */
si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
if (sctx->b.family == CHIP_STONEY &&
!(sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)) {
switch (desc->channel[0].size) {
case 32:
if (desc->nr_channels == 1) {
if (swap == V_0280A0_SWAP_STD)
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
else if (swap == V_0280A0_SWAP_ALT_REV)
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_A;
}
break;
case 16:
/* For 1-channel formats, use the superset thereof. */
if (desc->nr_channels <= 2) {
if (swap == V_0280A0_SWAP_STD ||
swap == V_0280A0_SWAP_STD_REV)
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_GR;
else
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_AR;
}
break;
case 11:
if (desc->nr_channels == 3) {
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_10_11_11;
surf->sx_blend_opt_epsilon = V_028758_11BIT_FORMAT;
}
break;
case 10:
if (desc->nr_channels == 4) {
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_2_10_10_10;
surf->sx_blend_opt_epsilon = V_028758_10BIT_FORMAT;
}
break;
case 8:
/* For 1 and 2-channel formats, use the superset thereof. */
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_8_8_8_8;
surf->sx_blend_opt_epsilon = V_028758_8BIT_FORMAT;
break;
case 5:
if (desc->nr_channels == 3) {
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_5_6_5;
surf->sx_blend_opt_epsilon = V_028758_6BIT_FORMAT;
} else if (desc->nr_channels == 4) {
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_1_5_5_5;
surf->sx_blend_opt_epsilon = V_028758_5BIT_FORMAT;
}
break;
case 4:
/* For 1 nad 2-channel formats, use the superset thereof. */
surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_4_4_4_4;
surf->sx_blend_opt_epsilon = V_028758_4BIT_FORMAT;
break;
}
}
surf->color_initialized = true;
}
@ -2515,8 +2648,6 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
uint32_t sx_ps_downconvert = 0;
uint32_t sx_blend_opt_epsilon = 0;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
@ -2567,29 +2698,18 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
if (sctx->b.chip_class >= VI)
radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
if (i == 1 && state->cbufs[0] &&
sctx->framebuffer.dirty_cbufs & (1 << 0)) {
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
cb->cb_color_info | tex->cb_color_info);
sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
i++;
}
for (; i < 8 ; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
if (sctx->b.family == CHIP_STONEY) {
radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 2);
radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
}
/* ZS buffer. */
if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;

3
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -1752,6 +1752,9 @@ bool si_update_shaders(struct si_context *sctx)
si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
}
if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
if (sctx->ps_db_shader_control != db_shader_control) {
sctx->ps_db_shader_control = db_shader_control;
si_mark_atom_dirty(sctx, &sctx->db_render_state);