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i965: enable accumulator update in PS kernel too on sandybridge

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Accumulator update flag must be set for implicit update on sandybridge.
(cherry picked from commit 8c31a4c3cf)
This commit is contained in:
Zhenyu Wang 2010-09-17 12:45:01 +08:00 • committed by Ian Romanick
parent 36722d7673
commit 0d5400519e
2 changed files with 6 additions and 0 deletions
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3
src/mesa/drivers/dri/i965/brw_wm_emit.c
View file

@ -1627,9 +1627,12 @@ static void spill_values( struct brw_wm_compile *c,
void brw_wm_emit( struct brw_wm_compile *c )
{
struct brw_compile *p = &c->func;
struct intel_context *intel = &p->brw->intel;
GLuint insn;
brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
if (intel->gen >= 6)
brw_set_acc_write_control(p, 1);
/* Check if any of the payload regs need to be spilled:
*/

3
src/mesa/drivers/dri/i965/brw_wm_glsl.c
View file

@ -711,6 +711,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
if (intel->gen >= 6)
brw_set_acc_write_control(p, 1);
for (i = 0; i < c->nr_fp_insns; i++) {
const struct prog_instruction *inst = &c->prog_instructions[i];
int dst_flags;