mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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aco: Initial GFX7 Support
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
This commit is contained in:
Daniel Schürmann
parent
3177346bfc
commit
0d42e4d7a0
4 changed files with 95 additions and 72 deletions
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@ -17,7 +17,9 @@ struct asm_context {
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// TODO: keep track of branch instructions referring blocks
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// and, when emitting the block, correct the offset in instr
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asm_context(Program* program) : program(program), chip_class(program->chip_class) {
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if (chip_class <= GFX9)
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if (chip_class <= GFX7)
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opcode = &instr_info.opcode_gfx7[0];
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else if (chip_class <= GFX9)
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opcode = &instr_info.opcode_gfx9[0];
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else if (chip_class == GFX10)
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opcode = &instr_info.opcode_gfx10[0];
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@ -145,9 +147,26 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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SMEM_instruction* smem = static_cast<SMEM_instruction*>(instr);
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bool soe = instr->operands.size() >= (!instr->definitions.empty() ? 3 : 4);
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bool is_load = !instr->definitions.empty();
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uint32_t encoding = 0;
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if (ctx.chip_class <= GFX7) {
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encoding = (0b11000 << 27);
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encoding |= opcode << 22;
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encoding |= instr->definitions.size() ? instr->definitions[0].physReg() << 15 : 0;
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encoding |= instr->operands.size() ? (instr->operands[0].physReg() >> 1) << 9 : 0;
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if (!instr->operands[1].isConstant() || instr->operands[1].constantValue() >= 1024) {
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encoding |= instr->operands[1].physReg().reg;
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} else {
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encoding |= instr->operands[1].constantValue() >> 2;
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encoding |= 1 << 8;
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}
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out.push_back(encoding);
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/* SMRD instructions can take a literal on GFX6 & GFX7 */
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if (instr->operands[1].isConstant() && instr->operands[1].constantValue() >= 1024)
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out.push_back(instr->operands[1].constantValue() >> 2);
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return;
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}
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if (ctx.chip_class <= GFX9) {
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encoding = (0b110000 << 26);
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assert(!smem->dlc); /* Device-level coherent is not supported on GFX9 and lower */
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@ -291,7 +310,7 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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encoding |= (mubuf->glc ? 1 : 0) << 14;
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encoding |= (mubuf->idxen ? 1 : 0) << 13;
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encoding |= (mubuf->offen ? 1 : 0) << 12;
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if (ctx.chip_class <= GFX9) {
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if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
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assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */
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encoding |= (mubuf->slc ? 1 : 0) << 17;
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} else if (ctx.chip_class >= GFX10) {
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@ -326,7 +345,7 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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encoding |= 0x0FFF & mtbuf->offset;
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encoding |= (img_format << 19); /* Handles both the GFX10 FORMAT and the old NFMT+DFMT */
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if (ctx.chip_class <= GFX9) {
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if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
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encoding |= opcode << 15;
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} else {
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encoding |= (opcode & 0x07) << 16; /* 3 LSBs of 4-bit OPCODE */
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@ -444,9 +463,9 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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case Format::EXP: {
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Export_instruction* exp = static_cast<Export_instruction*>(instr);
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uint32_t encoding;
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if (ctx.chip_class <= GFX9) {
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if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
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encoding = (0b110001 << 26);
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} else if (ctx.chip_class >= GFX10) {
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} else {
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encoding = (0b111110 << 26);
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}
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@ -473,12 +492,10 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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if ((uint16_t) instr->format & (uint16_t) Format::VOP2) {
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opcode = opcode + 0x100;
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} else if ((uint16_t) instr->format & (uint16_t) Format::VOP1) {
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if (ctx.chip_class <= GFX9) {
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if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9)
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opcode = opcode + 0x140;
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} else {
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/* RDNA ISA doc says this is 0x140, but that doesn't work */
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else
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opcode = opcode + 0x180;
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}
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} else if ((uint16_t) instr->format & (uint16_t) Format::VOPC) {
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opcode = opcode + 0x0;
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} else if ((uint16_t) instr->format & (uint16_t) Format::VINTRP) {
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@ -492,8 +509,13 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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encoding = (0b110101 << 26);
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}
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encoding |= opcode << 16;
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encoding |= (vop3->clamp ? 1 : 0) << 15;
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if (ctx.chip_class <= GFX7) {
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encoding |= opcode << 17;
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encoding |= (vop3->clamp ? 1 : 0) << 11;
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} else {
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encoding |= opcode << 16;
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encoding |= (vop3->clamp ? 1 : 0) << 15;
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}
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for (unsigned i = 0; i < 3; i++)
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encoding |= vop3->abs[i] << (8+i);
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for (unsigned i = 0; i < 4; i++)
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@ -515,6 +537,7 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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out.push_back(encoding);
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} else if (instr->isDPP()){
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assert(ctx.chip_class >= GFX8);
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/* first emit the instruction without the DPP operand */
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Operand dpp_op = instr->operands[0];
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instr->operands[0] = Operand(PhysReg{250}, v1);
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@ -1259,6 +1259,7 @@ uint16_t get_sgpr_alloc(Program *program, uint16_t addressable_sgprs);
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uint16_t get_addr_sgpr_from_waves(Program *program, uint16_t max_waves);
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typedef struct {
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const int16_t opcode_gfx7[static_cast<int>(aco_opcode::num_opcodes)];
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const int16_t opcode_gfx9[static_cast<int>(aco_opcode::num_opcodes)];
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const int16_t opcode_gfx10[static_cast<int>(aco_opcode::num_opcodes)];
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const std::bitset<static_cast<int>(aco_opcode::num_opcodes)> can_use_input_modifiers;
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@ -155,7 +155,7 @@ class Opcode(object):
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"""Class that represents all the information we have about the opcode
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NOTE: this must be kept in sync with aco_op_info
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"""
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def __init__(self, name, opcode_gfx9, opcode_gfx10, format, input_mod, output_mod):
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def __init__(self, name, opcode_gfx7, opcode_gfx9, opcode_gfx10, format, input_mod, output_mod):
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"""Parameters:
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- name is the name of the opcode (prepend nir_op_ for the enum name)
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@ -167,6 +167,7 @@ class Opcode(object):
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constant value of the opcode given the constant values of its inputs.
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"""
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assert isinstance(name, str)
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assert isinstance(opcode_gfx7, int)
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assert isinstance(opcode_gfx9, int)
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assert isinstance(opcode_gfx10, int)
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assert isinstance(format, Format)
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@ -174,6 +175,7 @@ class Opcode(object):
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assert isinstance(output_mod, bool)
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self.name = name
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self.opcode_gfx7 = opcode_gfx7
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self.opcode_gfx9 = opcode_gfx9
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self.opcode_gfx10 = opcode_gfx10
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self.input_mod = "1" if input_mod else "0"
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@ -184,14 +186,11 @@ class Opcode(object):
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# global dictionary of opcodes
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opcodes = {}
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# VOPC to GFX6 opcode translation map
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VOPC_GFX6 = [0] * 256
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def opcode(name, opcode_gfx9 = -1, opcode_gfx10 = -1, format = Format.PSEUDO, input_mod = False, output_mod = False):
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def opcode(name, opcode_gfx7 = -1, opcode_gfx9 = -1, opcode_gfx10 = -1, format = Format.PSEUDO, input_mod = False, output_mod = False):
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assert name not in opcodes
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opcodes[name] = Opcode(name, opcode_gfx9, opcode_gfx10, format, input_mod, output_mod)
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opcodes[name] = Opcode(name, opcode_gfx7, opcode_gfx9, opcode_gfx10, format, input_mod, output_mod)
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opcode("exp", 0, 0, format = Format.EXP)
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opcode("exp", 0, 0, 0, format = Format.EXP)
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opcode("p_parallelcopy")
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opcode("p_startpgm")
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opcode("p_phi")
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@ -302,7 +301,7 @@ SOP2 = {
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( -1, -1, -1, 0x2d, 0x36, "s_mul_hi_i32"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP2:
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opcode(name, gfx9, gfx10, Format.SOP2)
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opcode(name, gfx7, gfx9, gfx10, Format.SOP2)
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# SOPK instructions: 0 input (+ imm), 1 output + optional scc
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@ -338,7 +337,7 @@ SOPK = {
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( -1, -1, -1, -1, 0x1c, "s_subvector_loop_end"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPK:
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opcode(name, gfx9, gfx10, Format.SOPK)
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opcode(name, gfx7, gfx9, gfx10, Format.SOPK)
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# SOP1 instructions: 1 input, 1 output (+optional SCC)
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@ -416,7 +415,7 @@ SOP1 = {
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( -1, -1, -1, -1, -1, "p_constaddr"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP1:
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opcode(name, gfx9, gfx10, Format.SOP1)
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opcode(name, gfx7, gfx9, gfx10, Format.SOP1)
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# SOPC instructions: 2 inputs and 0 outputs (+SCC)
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@ -444,7 +443,7 @@ SOPC = {
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( -1, -1, 0x13, 0x13, 0x13, "s_cmp_lg_u64"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
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opcode(name, gfx9, gfx10, Format.SOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.SOPC)
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# SOPP instructions: 0 inputs (+optional scc/vcc), 0 outputs
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@ -491,7 +490,7 @@ SOPP = {
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( -1, -1, -1, -1, 0x26, "s_ttracedata_imm"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPP:
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opcode(name, gfx9, gfx10, Format.SOPP)
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opcode(name, gfx7, gfx9, gfx10, Format.SOPP)
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# SMEM instructions: sbase input (2 sgpr), potentially 2 offset inputs, 1 sdata input/output
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@ -585,7 +584,7 @@ SMEM = {
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( -1, -1, -1, 0xac, 0xac, "s_atomic_dec_x2"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SMEM:
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opcode(name, gfx9, gfx10, Format.SMEM)
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opcode(name, gfx7, gfx9, gfx10, Format.SMEM)
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# VOP2 instructions: 2 inputs, 1 output (+ optional vcc)
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@ -663,7 +662,7 @@ VOP2 = {
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( -1, -1, -1, -1, 0x3c, "v_pk_fmac_f16", False),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name, modifiers) in VOP2:
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opcode(name, gfx9, gfx10, Format.VOP2, modifiers, modifiers)
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opcode(name, gfx7, gfx9, gfx10, Format.VOP2, modifiers, modifiers)
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# VOP1 instructions: instructions with 1 input and 1 output
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@ -763,7 +762,7 @@ VOP1 = {
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( -1, -1, -1, -1, 0x68, "v_swaprel_b32", False, False),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod) in VOP1:
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opcode(name, gfx9, gfx10, Format.VOP1, in_mod, out_mod)
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opcode(name, gfx7, gfx9, gfx10, Format.VOP1, in_mod, out_mod)
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# VOPC instructions:
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@ -777,29 +776,29 @@ VOPC_CLASS = {
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(0xb8, 0xb8, 0x13, 0x13, 0xb8, "v_cmpx_class_f64"),
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}
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for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in VOPC_CLASS:
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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COMPF = ["f", "lt", "eq", "le", "gt", "lg", "ge", "o", "u", "nge", "nlg", "ngt", "nle", "neq", "nlt", "tru"]
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for i in range(8):
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0x20+i, 0x20+i, 0xc8+i, "v_cmp_"+COMPF[i]+"_f16")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0x30+i, 0x30+i, 0xd8+i, "v_cmpx_"+COMPF[i]+"_f16")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0x28+i, 0x28+i, 0xe8+i, "v_cmp_"+COMPF[i+8]+"_f16")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0x38+i, 0x38+i, 0xf8+i, "v_cmpx_"+COMPF[i+8]+"_f16")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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for i in range(16):
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x00+i, 0x00+i, 0x40+i, 0x40+i, 0x00+i, "v_cmp_"+COMPF[i]+"_f32")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x10+i, 0x10+i, 0x50+i, 0x50+i, 0x10+i, "v_cmpx_"+COMPF[i]+"_f32")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x20+i, 0x20+i, 0x60+i, 0x60+i, 0x20+i, "v_cmp_"+COMPF[i]+"_f64")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x30+i, 0x30+i, 0x70+i, 0x70+i, 0x30+i, "v_cmpx_"+COMPF[i]+"_f64")
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opcode(name, gfx9, gfx10, Format.VOPC, True, False)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
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# GFX_6_7
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x40+i, 0x40+i, -1, -1, -1, "v_cmps_"+COMPF[i]+"_f32")
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x50+i, 0x50+i, -1, -1, -1, "v_cmpsx_"+COMPF[i]+"_f32")
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@ -811,41 +810,41 @@ COMPI = ["f", "lt", "eq", "le", "gt", "lg", "ge", "tru"]
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# GFX_8_9
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for i in [0,7]: # only 0 and 7
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xa0+i, 0xa0+i, -1, "v_cmp_"+COMPI[i]+"_i16")
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opcode(name, gfx9, gfx10, Format.VOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xb0+i, 0xb0+i, -1, "v_cmpx_"+COMPI[i]+"_i16")
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opcode(name, gfx9, gfx10, Format.VOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xa8+i, 0xa8+i, -1, "v_cmp_"+COMPI[i]+"_u16")
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opcode(name, gfx9, gfx10, Format.VOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xb8+i, 0xb8+i, -1, "v_cmpx_"+COMPI[i]+"_u16")
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opcode(name, gfx9, gfx10, Format.VOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
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for i in range(1, 7): # [1..6]
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xa0+i, 0xa0+i, 0x88+i, "v_cmp_"+COMPI[i]+"_i16")
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opcode(name, gfx9, gfx10, Format.VOPC)
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
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(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xb0+i, 0xb0+i, 0x98+i, "v_cmpx_"+COMPI[i]+"_i16")
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opcode(name, gfx9, gfx10, Format.VOPC)
|
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opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xa8+i, 0xa8+i, 0xa8+i, "v_cmp_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, 0xb8+i, 0xb8+i, 0xb8+i, "v_cmpx_"+COMPI[i]+"_u16")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
|
||||
for i in range(8):
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x80+i, 0x80+i, 0xc0+i, 0xc0+i, 0x80+i, "v_cmp_"+COMPI[i]+"_i32")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0x90+i, 0x90+i, 0xd0+i, 0xd0+i, 0x90+i, "v_cmpx_"+COMPI[i]+"_i32")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xa0+i, 0xa0+i, 0xe0+i, 0xe0+i, 0xa0+i, "v_cmp_"+COMPI[i]+"_i64")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xb0+i, 0xb0+i, 0xf0+i, 0xf0+i, 0xb0+i, "v_cmpx_"+COMPI[i]+"_i64")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xc0+i, 0xc0+i, 0xc8+i, 0xc8+i, 0xc0+i, "v_cmp_"+COMPI[i]+"_u32")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xd0+i, 0xd0+i, 0xd8+i, 0xd8+i, 0xd0+i, "v_cmpx_"+COMPI[i]+"_u32")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xe0+i, 0xe0+i, 0xe8+i, 0xe8+i, 0xe0+i, "v_cmp_"+COMPI[i]+"_u64")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
(gfx6, gfx7, gfx8, gfx9, gfx10, name) = (0xf0+i, 0xf0+i, 0xf8+i, 0xf8+i, 0xf0+i, "v_cmpx_"+COMPI[i]+"_u64")
|
||||
opcode(name, gfx9, gfx10, Format.VOPC)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOPC)
|
||||
|
||||
|
||||
# VOPP instructions: packed 16bit instructions - 1 or 2 inputs and 1 output
|
||||
|
|
@ -876,7 +875,7 @@ VOPP = {
|
|||
# note that these are only supported on gfx9+ so we'll need to distinguish between gfx8 and gfx9 here
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (-1, -1, -1, code, code, name)
|
||||
for (code, name) in VOPP:
|
||||
opcode(name, code, code, Format.VOP3P)
|
||||
opcode(name, -1, code, code, Format.VOP3P)
|
||||
|
||||
|
||||
# VINTERP instructions:
|
||||
|
|
@ -887,7 +886,7 @@ VINTRP = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (code, code, code, code, code, name)
|
||||
for (code, name) in VINTRP:
|
||||
opcode(name, code, code, Format.VINTRP)
|
||||
opcode(name, code, code, code, Format.VINTRP)
|
||||
|
||||
# VOP3 instructions: 3 inputs, 1 output
|
||||
# VOP3b instructions: have a unique scalar output, e.g. VOP2 with vcc out
|
||||
|
|
@ -1015,7 +1014,7 @@ VOP3 = {
|
|||
# TODO: many 16bit instructions moved from VOP2 to VOP3 on GFX10
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod) in VOP3:
|
||||
opcode(name, gfx9, gfx10, Format.VOP3A, in_mod, out_mod)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.VOP3A, in_mod, out_mod)
|
||||
|
||||
|
||||
# DS instructions: 3 inputs (1 addr, 2 data), 1 output
|
||||
|
|
@ -1177,7 +1176,7 @@ DS = {
|
|||
( -1, 0xff, 0xff, 0xff, 0xff, "ds_read_b128"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in DS:
|
||||
opcode(name, gfx9, gfx10, Format.DS)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.DS)
|
||||
|
||||
# MUBUF instructions:
|
||||
MUBUF = {
|
||||
|
|
@ -1262,7 +1261,7 @@ MUBUF = {
|
|||
( -1, -1, -1, -1, 0x72, "buffer_gl1_inv"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MUBUF:
|
||||
opcode(name, gfx9, gfx10, Format.MUBUF)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.MUBUF)
|
||||
|
||||
MTBUF = {
|
||||
(0x00, 0x00, 0x00, 0x00, 0x00, "tbuffer_load_format_x"),
|
||||
|
|
@ -1283,7 +1282,7 @@ MTBUF = {
|
|||
( -1, -1, 0x0f, 0x0f, 0x0f, "tbuffer_store_format_d16_xyzw"),
|
||||
}
|
||||
for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MTBUF:
|
||||
opcode(name, gfx9, gfx10, Format.MTBUF)
|
||||
opcode(name, gfx7, gfx9, gfx10, Format.MTBUF)
|
||||
|
||||
|
||||
IMAGE = {
|
||||
|
|
@ -1302,7 +1301,7 @@ IMAGE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (code, code, code, code, code, name)
|
||||
for (code, name) in IMAGE:
|
||||
opcode(name, code, code, Format.MIMG)
|
||||
opcode(name, code, code, code, Format.MIMG)
|
||||
|
||||
IMAGE_ATOMIC = {
|
||||
(0x0f, 0x0f, 0x10, "image_atomic_swap"),
|
||||
|
|
@ -1326,7 +1325,7 @@ IMAGE_ATOMIC = {
|
|||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (gfx6, gfx7, gfx89, gfx89, ???, name)
|
||||
# gfx7 and gfx10 opcodes are the same here
|
||||
for (gfx6, gfx7, gfx89, name) in IMAGE_ATOMIC:
|
||||
opcode(name, gfx89, gfx7, Format.MIMG)
|
||||
opcode(name, gfx7, gfx89, gfx7, Format.MIMG)
|
||||
|
||||
IMAGE_SAMPLE = {
|
||||
(0x20, "image_sample"),
|
||||
|
|
@ -1372,7 +1371,7 @@ IMAGE_SAMPLE = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (code, code, code, code, code, name)
|
||||
for (code, name) in IMAGE_SAMPLE:
|
||||
opcode(name, code, code, Format.MIMG)
|
||||
opcode(name, code, code, code, Format.MIMG)
|
||||
|
||||
IMAGE_GATHER4 = {
|
||||
(0x40, "image_gather4"),
|
||||
|
|
@ -1405,7 +1404,7 @@ IMAGE_GATHER4 = {
|
|||
}
|
||||
# (gfx6, gfx7, gfx8, gfx9, gfx10, name) = (code, code, code, code, code, name)
|
||||
for (code, name) in IMAGE_GATHER4:
|
||||
opcode(name, code, code, Format.MIMG)
|
||||
opcode(name, code, code, code, Format.MIMG)
|
||||
|
||||
|
||||
FLAT = {
|
||||
|
|
@ -1466,7 +1465,7 @@ FLAT = {
|
|||
(0x60, -1, 0x60, "flat_atomic_fmax_x2"),
|
||||
}
|
||||
for (gfx7, gfx8, gfx10, name) in FLAT:
|
||||
opcode(name, gfx8, gfx10, Format.FLAT)
|
||||
opcode(name, gfx7, gfx8, gfx10, Format.FLAT)
|
||||
|
||||
GLOBAL = {
|
||||
#GFX8_9, GFX10
|
||||
|
|
@ -1526,7 +1525,7 @@ GLOBAL = {
|
|||
( -1, 0x60, "global_atomic_fmax_x2"),
|
||||
}
|
||||
for (gfx8, gfx10, name) in GLOBAL:
|
||||
opcode(name, gfx8, gfx10, Format.GLOBAL)
|
||||
opcode(name, -1, gfx8, gfx10, Format.GLOBAL)
|
||||
|
||||
SCRATCH = {
|
||||
#GFX8_9, GFX10
|
||||
|
|
@ -1554,7 +1553,7 @@ SCRATCH = {
|
|||
(0x25, 0x25, "scratch_load_short_d16_hi"),
|
||||
}
|
||||
for (gfx8, gfx10, name) in SCRATCH:
|
||||
opcode(name, gfx8, gfx10, Format.SCRATCH)
|
||||
opcode(name, -1, gfx8, gfx10, Format.SCRATCH)
|
||||
|
||||
# check for duplicate opcode numbers
|
||||
for ver in ['gfx9', 'gfx10']:
|
||||
|
|
|
|||
|
|
@ -28,11 +28,6 @@ template = """\
|
|||
|
||||
namespace aco {
|
||||
|
||||
const unsigned VOPC_to_GFX6[256] = {
|
||||
% for code in VOPC_GFX6:
|
||||
${code},
|
||||
% endfor
|
||||
};
|
||||
|
||||
<%
|
||||
opcode_names = sorted(opcodes.keys())
|
||||
|
|
@ -41,6 +36,11 @@ can_use_output_modifiers = "".join([opcodes[name].output_mod for name in reverse
|
|||
%>
|
||||
|
||||
extern const aco::Info instr_info = {
|
||||
.opcode_gfx7 = {
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx7},
|
||||
% endfor
|
||||
},
|
||||
.opcode_gfx9 = {
|
||||
% for name in opcode_names:
|
||||
${opcodes[name].opcode_gfx9},
|
||||
|
|
@ -68,7 +68,7 @@ extern const aco::Info instr_info = {
|
|||
}
|
||||
"""
|
||||
|
||||
from aco_opcodes import opcodes, VOPC_GFX6
|
||||
from aco_opcodes import opcodes
|
||||
from mako.template import Template
|
||||
|
||||
print(Template(template).render(opcodes=opcodes, VOPC_GFX6=VOPC_GFX6))
|
||||
print(Template(template).render(opcodes=opcodes))
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue