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panfrost/midgard: Remove opt_copy_prop_tex
Eventually this should be replaced by proper tex RA / not emitting so many silly moves to begin with / better general copy prop. For now remove it since it breaks things. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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1 changed files with 0 additions and 50 deletions
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@ -2225,55 +2225,6 @@ midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
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return progress;
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}
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static bool
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midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
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{
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bool progress = false;
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mir_foreach_instr_in_block_safe(block, ins) {
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if (ins->type != TAG_ALU_4) continue;
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if (!OP_IS_MOVE(ins->alu.op)) continue;
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unsigned from = ins->ssa_args.src1;
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unsigned to = ins->ssa_args.dest;
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/* Make sure it's simple enough for us to handle */
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if (from >= SSA_FIXED_MINIMUM) continue;
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if (from >= ctx->func->impl->ssa_alloc) continue;
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if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
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if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
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bool eliminated = false;
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mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
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/* The texture registers are not SSA so be careful.
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* Conservatively, just stop if we hit a texture op
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* (even if it may not write) to where we are */
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if (v->type != TAG_ALU_4)
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break;
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if (v->ssa_args.dest == from) {
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/* We don't want to track partial writes ... */
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if (v->mask == 0xF) {
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v->ssa_args.dest = to;
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eliminated = true;
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}
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break;
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}
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}
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if (eliminated)
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mir_remove_instruction(ins);
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progress |= eliminated;
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}
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return progress;
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}
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/* The following passes reorder MIR instructions to enable better scheduling */
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static void
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@ -2699,7 +2650,6 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
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mir_foreach_block(ctx, block) {
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progress |= midgard_opt_pos_propagate(ctx, block);
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progress |= midgard_opt_copy_prop(ctx, block);
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progress |= midgard_opt_copy_prop_tex(ctx, block);
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progress |= midgard_opt_dead_code_eliminate(ctx, block);
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}
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} while (progress);
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