diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 2960f83895c..30eeea2f014 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -3589,6 +3589,7 @@ struct anv_graphics_pipeline {
       uint32_t                                  streamout_state[5];
       uint32_t                                  gs[10];
       uint32_t                                  te[4];
+      uint32_t                                  vfg[4];
    } partial;
 };
 
diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c
index 9ce99ef6be6..3d4ec697751 100644
--- a/src/intel/vulkan/genX_gfx_state.c
+++ b/src/intel/vulkan/genX_gfx_state.c
@@ -1119,30 +1119,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 #if GFX_VERx10 >= 125
    if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE)) {
-      anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VFG), vfg) {
-         /* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
-         vfg.DistributionMode =
-            anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ? RR_STRICT :
-                                                                      RR_FREE;
-         vfg.DistributionGranularity = BatchLevelGranularity;
-         /* Wa_14014890652 */
-         if (intel_device_info_is_dg2(cmd_buffer->device->info))
-            vfg.GranularityThresholdDisable = 1;
+      anv_batch_emit_merge(&cmd_buffer->batch, GENX(3DSTATE_VFG),
+                           pipeline->partial.vfg, vfg) {
          vfg.ListCutIndexEnable = dyn->ia.primitive_restart_enable;
-         /* 192 vertices for TRILIST_ADJ */
-         vfg.ListNBatchSizeScale = 0;
-         /* Batch size of 384 vertices */
-         vfg.List3BatchSizeScale = 2;
-         /* Batch size of 128 vertices */
-         vfg.List2BatchSizeScale = 1;
-         /* Batch size of 128 vertices */
-         vfg.List1BatchSizeScale = 2;
-         /* Batch size of 256 vertices for STRIP topologies */
-         vfg.StripBatchSizeScale = 3;
-         /* 192 control points for PATCHLIST_3 */
-         vfg.PatchBatchSizeScale = 1;
-         /* 192 control points for PATCHLIST_3 */
-         vfg.PatchBatchSizeMultiplier = 31;
       }
    }
 #endif
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index a3cf849c9cc..8174ab54b8f 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -303,6 +303,36 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline,
       sgvs.XP2ElementOffset            = drawid_slot;
    }
 #endif
+
+#if GFX_VERx10 >= 125
+   struct anv_device *device = pipeline->base.base.device;
+   struct GENX(3DSTATE_VFG) vfg = {
+      GENX(3DSTATE_VFG_header),
+      /* If 3DSTATE_TE: TE Enable == 1 then RR_STRICT else RR_FREE*/
+      .DistributionMode =
+         anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ? RR_STRICT :
+         RR_FREE,
+      .DistributionGranularity = BatchLevelGranularity,
+   };
+   /* Wa_14014890652 */
+   if (intel_device_info_is_dg2(device->info))
+      vfg.GranularityThresholdDisable = 1;
+   /* 192 vertices for TRILIST_ADJ */
+   vfg.ListNBatchSizeScale = 0;
+   /* Batch size of 384 vertices */
+   vfg.List3BatchSizeScale = 2;
+   /* Batch size of 128 vertices */
+   vfg.List2BatchSizeScale = 1;
+   /* Batch size of 128 vertices */
+   vfg.List1BatchSizeScale = 2;
+   /* Batch size of 256 vertices for STRIP topologies */
+   vfg.StripBatchSizeScale = 3;
+   /* 192 control points for PATCHLIST_3 */
+   vfg.PatchBatchSizeScale = 1;
+   /* 192 control points for PATCHLIST_3 */
+   vfg.PatchBatchSizeMultiplier = 31;
+   GENX(3DSTATE_VFG_pack)(NULL, pipeline->partial.vfg, &vfg);
+#endif
 }
 
 void