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intel: use generated helpers for Wa_1508744258

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iris_disable_rhwo_optimization can only apply on gfxver 12.0, and has
a version check to that affect.  Add an assertion to warn us if the
workaround ever applies to another version.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21742>
This commit is contained in:
Mark Janes 2023-02-08 15:47:20 -08:00 • committed by Marge Bot
parent 256f64dc45
commit 0ce595a89a
5 changed files with 28 additions and 21 deletions
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28
src/gallium/drivers/iris/iris_resolve.c
View file

@ -518,17 +518,19 @@ iris_resolve_color(struct iris_context *ice,
iris_emit_end_of_pipe_sync(batch, "color resolve: pre-flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH);
/* Wa_1508744258
*
* Disable RHWO by setting 0x7010[14] by default except during resolve
* pass.
*
* We implement global disabling of the RHWO optimization during
* iris_init_render_context. We toggle it around the blorp resolve call.
*/
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
batch->screen->vtbl.disable_rhwo_optimization(batch, false);
if (intel_needs_workaround(batch->screen->devinfo, 1508744258)) {
/* The suggested workaround is:
*
* Disable RHWO by setting 0x7010[14] by default except during resolve
* pass.
*
* We implement global disabling of the RHWO optimization during
* iris_init_render_context. We toggle it around the blorp resolve call.
*/
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
batch->screen->vtbl.disable_rhwo_optimization(batch, false);
}
iris_batch_sync_region_start(batch);
struct blorp_batch blorp_batch;
@ -541,7 +543,9 @@ iris_resolve_color(struct iris_context *ice,
iris_emit_end_of_pipe_sync(batch, "color resolve: post-flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH);
batch->screen->vtbl.disable_rhwo_optimization(batch, true);
if (intel_needs_workaround(batch->screen->devinfo, 1508744258)) {
batch->screen->vtbl.disable_rhwo_optimization(batch, true);
}
iris_batch_sync_region_end(batch);
}

7
src/gallium/drivers/iris/iris_state.c
View file

@ -1078,6 +1078,7 @@ init_aux_map_state(struct iris_batch *batch);
static void
iris_disable_rhwo_optimization(struct iris_batch *batch, bool disable)
{
assert(batch->screen->devinfo->verx10 == 120);
#if GFX_VERx10 == 120
iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
c1.RCCRHWOOptimizationDisable = disable;
@ -1228,8 +1229,8 @@ iris_init_render_context(struct iris_batch *batch)
}
#endif
#if GFX_VERx10 == 120
/* Wa_1508744258
#if INTEL_NEEDS_WORKAROUND_1508744258
/* The suggested workaround is:
*
* Disable RHWO by setting 0x7010[14] by default except during resolve
* pass.
@ -1244,7 +1245,9 @@ iris_init_render_context(struct iris_batch *batch)
* field in the 3DSTATE_PS instruction).
*/
iris_disable_rhwo_optimization(batch, true);
#endif
#if GFX_VERx10 == 120
/* Wa_1806527549 says to disable the following HiZ optimization when the
* depth buffer is D16_UNORM. We've found the WA to help with more depth
* buffer configurations however, so we always disable it just to be safe.

3
src/intel/vulkan/anv_blorp.c
View file

@ -1252,7 +1252,8 @@ exec_ccs_op(struct anv_cmd_buffer *cmd_buffer,
case ISL_AUX_OP_FULL_RESOLVE:
case ISL_AUX_OP_PARTIAL_RESOLVE: {
/* Wa_1508744258: Enable RHWO optimization for resolves */
const bool enable_rhwo_opt = cmd_buffer->device->info->verx10 == 120;
const bool enable_rhwo_opt =
intel_needs_workaround(cmd_buffer->device->info, 1508744258);
if (enable_rhwo_opt)
cmd_buffer->state.pending_rhwo_optimization_enabled = true;

5
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1761,7 +1761,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
ALWAYS_INLINE void
genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
{
#if GFX_VERx10 == 120
#if INTEL_NEEDS_WA_1508744258
/* If we're changing the state of the RHWO optimization, we need to have
* sb_stall+cs_stall.
*/
@ -1809,8 +1809,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.current_pipeline,
bits);
#if GFX_VERx10 == 120
/* Wa_1508744258 handling */
#if INTEL_NEEDS_WA_1508744258
if (rhwo_opt_change) {
anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), c1) {
c1.RCCRHWOOptimizationDisable =

6
src/intel/vulkan/genX_state.c
View file

@ -467,10 +467,10 @@ init_render_queue_state(struct anv_queue *queue)
reg.HZDepthTestLEGEOptimizationDisable = true;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
#endif
/* Wa_1508744258
*
* Disable RHWO by setting 0x7010[14] by default except during resolve
#if INTEL_NEEDS_WA_1508744258
/* Disable RHWO by setting 0x7010[14] by default except during resolve
* pass.
*
* We implement global disabling of the optimization here and we toggle it