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intel/compiler: Create and use struct for VS thread payload

Browse source 
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira 2022-08-21 21:22:12 -07:00 • committed by Marge Bot
parent 19c6e1b447
commit 0ca65b3c4c
4 changed files with 30 additions and 13 deletions
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11
src/intel/compiler/brw_fs.cpp
View file

@ -5852,15 +5852,6 @@ fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) con
fprintf(file, "\n");
}
void
fs_visitor::setup_vs_payload()
{
thread_payload &payload = this->payload();
/* R0: thread header, R1: urb handles */
payload.num_regs = 2;
}
void
fs_visitor::setup_gs_payload()
{
@ -6550,7 +6541,7 @@ fs_visitor::run_vs()
{
assert(stage == MESA_SHADER_VERTEX);
setup_vs_payload();
payload_ = new vs_thread_payload();
emit_nir_code();

12
src/intel/compiler/brw_fs.h
View file

@ -93,6 +93,12 @@ struct thread_payload {
virtual ~thread_payload() = default;
};
struct vs_thread_payload : public thread_payload {
vs_thread_payload();
fs_reg urb_handles;
};
struct tcs_thread_payload : public thread_payload {
tcs_thread_payload(const fs_visitor &v);
@ -173,7 +179,6 @@ public:
bool run_mesh(bool allow_spilling);
void optimize();
void allocate_registers(bool allow_spilling);
void setup_vs_payload();
void setup_gs_payload();
void setup_cs_payload();
bool fixup_sends_duplicate_payload();
@ -438,6 +443,11 @@ public:
return *this->payload_;
}
vs_thread_payload &vs_payload() {
assert(stage == MESA_SHADER_VERTEX);
return *static_cast<vs_thread_payload *>(this->payload_);
}
tcs_thread_payload &tcs_payload() {
assert(stage == MESA_SHADER_TESS_CTRL);
return *static_cast<tcs_thread_payload *>(this->payload_);

7
src/intel/compiler/brw_fs_thread_payload.cpp
View file

@ -25,6 +25,13 @@
using namespace brw;
vs_thread_payload::vs_thread_payload()
{
urb_handles = retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD);
num_regs = 2;
}
tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
{
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);

13
src/intel/compiler/brw_fs_visitor.cpp
View file

@ -770,10 +770,19 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
fs_reg sources[8];
fs_reg urb_handle;
if (stage == MESA_SHADER_TESS_EVAL)
switch (stage) {
case MESA_SHADER_VERTEX:
urb_handle = vs_payload().urb_handles;
break;
case MESA_SHADER_TESS_EVAL:
urb_handle = tes_payload().urb_output;
else
break;
case MESA_SHADER_GEOMETRY:
urb_handle = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD));
break;
default:
unreachable("invalid stage");
}
int header_size = 1;
fs_reg per_slot_offsets;