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r300: set up r5xx fragment shader; clear still broken

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This commit is contained in:
Joakim Sindholt 2009-01-29 20:24:34 +01:00 • committed by Corbin Simpson
parent c199f33032
commit 0c9d2bbb12
3 changed files with 29 additions and 61 deletions
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6
src/gallium/drivers/r300/r300_emit.c
View file

@ -62,11 +62,11 @@ void r300_emit_dsa_state(struct r300_context* r300,
struct r300_screen* r300screen =
(struct r300_screen*)r300->context.screen;
CS_LOCALS(r300);
BEGIN_CS(r300screen->caps->is_r500 ? 12 : 8);
BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8);
OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function);
/* XXX figure out the r300 counterpart for this */
if (r300screen->caps->is_r500) {
OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference);
/* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */
}
OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
OUT_CS(dsa->z_buffer_control);
@ -74,7 +74,7 @@ void r300_emit_dsa_state(struct r300_context* r300,
OUT_CS(dsa->stencil_ref_mask);
OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top);
if (r300screen->caps->is_r500) {
OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf);
/* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */
}
END_CS;
}

2
src/gallium/drivers/r300/r300_reg.h
View file

@ -3004,7 +3004,7 @@ enum {
# define R500_US_CODE_RANGE_ADDR(x) (x << 0)
# define R500_US_CODE_RANGE_SIZE(x) (x << 16)
#define R500_US_CONFIG 0x4600
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 0)
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
#define R500_US_FC_ADDR_0 0xa000
# define R500_FC_BOOL_ADDR(x) (x << 0)
# define R500_FC_INT_ADDR(x) (x << 8)

82
src/gallium/drivers/r300/r300_surface.c
View file

@ -42,7 +42,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
" dimensions %dx%d, color 0x%x\n",
dest, x, y, w, h, color);
BEGIN_CS((caps->is_r500) ? 367 : 322);
BEGIN_CS((caps->is_r500) ? 300 : 322);
R300_PACIFY;
OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
R300_PACIFY;
@ -122,17 +122,6 @@ OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED);
OUT_CS_REG(R300_US_W_FMT, 0x00000001);
OUT_CS_REG(R300_US_CONFIG, 0x00000000);
OUT_CS_REG(R300_US_PIXSIZE, 0x00000000);
OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000);
OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000);
OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000);
OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000);
OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00000000);
OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00000000);
OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x00000000);
OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00000000);
OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x00000000);
OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
@ -149,9 +138,6 @@ for (i = 0; i < 8; i++)
OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
OUT_CS_REG(R300_ZB_CNTL, 0x00000010);
OUT_CS_REG(R300_ZB_ZSTENCILCNTL, 0x00038038);
OUT_CS_REG(R300_ZB_STENCILREFMASK, 0x00FFFF00);
OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
@ -182,7 +168,6 @@ OUT_CS_32F(1.0);
OUT_CS_32F(0.0);
OUT_CS_32F(1.0);
OUT_CS_32F(0.0);
OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000);
OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000);
OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
@ -200,53 +185,36 @@ if (caps->is_r500) {
}
R300_PACIFY;
OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_CS_REG(R500_US_PIXSIZE, 0x00000000);
OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(1));
OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(1));
OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0));
R300_PACIFY;
OUT_CS_REG(R500_US_CMN_INST_0,
R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP);
OUT_CS_REG(R500_US_ALU_RGB_ADDR_0,
R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) |
R500_RGB_ADDR2_CONST);
OUT_CS_REG(R500_US_ALU_ALPHA_ADDR_0,
R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(0) |
R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) |
R500_ALPHA_ADDR2_CONST);
OUT_CS_REG(R500_US_ALU_RGB_INST_0,
R500_ALU_RGB_SEL_A_SRC0 |
R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC0 |
R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G |
R500_ALU_RGB_G_SWIZ_B_B);
OUT_CS_REG(R500_US_ALU_ALPHA_INST_0,
R500_ALPHA_OP_CMP |
R500_ALPHA_SWIZ_A_A |
R500_ALPHA_SWIZ_B_A);
OUT_CS_REG(R500_US_ALU_RGBA_INST_0,
R500_ALU_RGBA_OP_CMP |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0);
OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
0 | R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A);
OUT_CS_REG(R500_GA_US_VECTOR_DATA,
R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0);
} else {
OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
for (i = 0; i < 8; i++) {