diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index e1694b46e8e..af9ed36c8a2 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -599,7 +599,7 @@ get_copy_region_aux_settings(struct iris_context *ice, } FALLTHROUGH; case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: { + case ISL_AUX_USAGE_FCV_CCS_E: { /* If our source doesn't have any unresolved color, report an aux * usage of ISL_AUX_USAGE_NONE. This way, texturing won't even look * at the aux surface and we can save some bandwidth. diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 586df0599f5..c4cb48c3947 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -54,7 +54,7 @@ disable_rb_aux_buffer(struct iris_context *ice, /* We only need to worry about color compression and fast clears. */ if (tex_res->aux.usage != ISL_AUX_USAGE_CCS_D && tex_res->aux.usage != ISL_AUX_USAGE_CCS_E && - tex_res->aux.usage != ISL_AUX_USAGE_GFX12_CCS_E) + tex_res->aux.usage != ISL_AUX_USAGE_FCV_CCS_E) return false; for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) { @@ -986,7 +986,7 @@ iris_resource_texture_aux_usage(struct iris_context *ice, return res->aux.usage; case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: /* If we don't have any unresolved color, report an aux usage of * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the * aux surface and we can save some bandwidth. @@ -1049,7 +1049,7 @@ iris_image_view_aux_usage(struct iris_context *ice, !iris_has_invalid_primary(res, level, 1, 0, INTEL_REMAINING_LAYERS)) return ISL_AUX_USAGE_NONE; - if (res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E) + if (res->aux.usage == ISL_AUX_USAGE_FCV_CCS_E) return res->aux.usage; return ISL_AUX_USAGE_NONE; @@ -1181,7 +1181,7 @@ iris_resource_render_aux_usage(struct iris_context *ice, case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: /* Disable CCS for some cases of texture-view rendering. On gfx12, HW * may convert some subregions of shader output to fast-cleared blocks * if CCS is enabled and the shader output matches the clear color. diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 9c602aaeb99..e31d51154ab 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -851,7 +851,7 @@ iris_resource_configure_aux(struct iris_screen *screen, res->aux.usage = ISL_AUX_USAGE_STC_CCS; } else if (want_ccs_e_for_format(devinfo, res->surf.format)) { res->aux.usage = devinfo->ver < 12 ? - ISL_AUX_USAGE_CCS_E : ISL_AUX_USAGE_GFX12_CCS_E; + ISL_AUX_USAGE_CCS_E : ISL_AUX_USAGE_FCV_CCS_E; } else { assert(isl_format_supports_ccs_d(devinfo, res->surf.format)); res->aux.usage = ISL_AUX_USAGE_CCS_D; @@ -875,7 +875,7 @@ iris_resource_configure_aux(struct iris_screen *screen, break; case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: case ISL_AUX_USAGE_STC_CCS: case ISL_AUX_USAGE_MC: if (imported) { diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 53b5ad23daf..0aaff4eac95 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -2736,7 +2736,7 @@ iris_create_sampler_view(struct pipe_context *ctx, if ((isv->res->aux.usage == ISL_AUX_USAGE_CCS_D || isv->res->aux.usage == ISL_AUX_USAGE_CCS_E || - isv->res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E) && + isv->res->aux.usage == ISL_AUX_USAGE_FCV_CCS_E) && !isl_format_supports_ccs_e(devinfo, isv->view.format)) { aux_usages = 1 << ISL_AUX_USAGE_NONE; } else if (isl_aux_usage_has_hiz(isv->res->aux.usage) && @@ -2976,7 +2976,7 @@ iris_create_surface(struct pipe_context *ctx, unsigned aux_usages = 0; if ((res->aux.usage == ISL_AUX_USAGE_CCS_E || - res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E) && + res->aux.usage == ISL_AUX_USAGE_FCV_CCS_E) && !isl_format_supports_ccs_e(devinfo, view->format)) { aux_usages = 1 << ISL_AUX_USAGE_NONE; } else { diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index d7e7a42dd48..c1ee720ad65 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2434,7 +2434,7 @@ blorp_blit_supports_compute(struct blorp_context *blorp, return false; if (blorp->isl_dev->info->ver >= 12) { - return dst_aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + return dst_aux_usage == ISL_AUX_USAGE_FCV_CCS_E || dst_aux_usage == ISL_AUX_USAGE_CCS_E || dst_aux_usage == ISL_AUX_USAGE_NONE; } else if (blorp->isl_dev->info->ver >= 7) { @@ -2453,7 +2453,7 @@ blorp_blitter_supports_aux(const struct intel_device_info *devinfo, case ISL_AUX_USAGE_NONE: return true; case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: return devinfo->verx10 >= 125; default: return false; @@ -2958,7 +2958,7 @@ blorp_copy(struct blorp_batch *batch, params.src.aux_usage == ISL_AUX_USAGE_MCS || params.src.aux_usage == ISL_AUX_USAGE_MCS_CCS || params.src.aux_usage == ISL_AUX_USAGE_CCS_E || - params.src.aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + params.src.aux_usage == ISL_AUX_USAGE_FCV_CCS_E || params.src.aux_usage == ISL_AUX_USAGE_STC_CCS); blorp_copy_get_formats(isl_dev, ¶ms.src.surf, ¶ms.dst.surf, diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 5a166100f96..89ae7f89f8e 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -527,7 +527,7 @@ blorp_clear_supports_compute(struct blorp_context *blorp, if (color_write_disable != 0 || blend_enabled) return false; if (blorp->isl_dev->info->ver >= 12) { - return aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + return aux_usage == ISL_AUX_USAGE_FCV_CCS_E || aux_usage == ISL_AUX_USAGE_CCS_E || aux_usage == ISL_AUX_USAGE_NONE; } else { diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 6011592e289..8a39f1b2ecb 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -2401,7 +2401,7 @@ xy_aux_mode(const struct brw_blorp_surface_info *info) { switch (info->aux_usage) { case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: return XY_CCS_E; case ISL_AUX_USAGE_NONE: return XY_NONE; diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index f0b943fabd9..a2eb0c6880f 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -779,16 +779,18 @@ enum isl_aux_usage { */ ISL_AUX_USAGE_CCS_E, - /** Single-sample lossless color compression on Tigerlake + /** Single-sample lossless color compression with fast clear optimization * - * This is identical to ISL_AUX_USAGE_CCS_E except it also encodes the - * Tigerlake quirk about regular render writes possibly fast-clearing - * blocks in the surface. + * Introduced on Tigerlake, this is identical to ISL_AUX_USAGE_CCS_E except + * it also encodes a feature about regular render writes possibly + * fast-clearing blocks in the surface. In the Alchemist docs, the name of + * the feature is easier to find. In the 3DSTATE_3D_MODE packet, it is + * referred to as "Fast Clear Optimization (FCV)". * * @invariant The surface is a color surface * @invariant isl_surf::samples == 1 */ - ISL_AUX_USAGE_GFX12_CCS_E, + ISL_AUX_USAGE_FCV_CCS_E, /** Media color compression * @@ -2202,7 +2204,7 @@ isl_aux_usage_has_ccs(enum isl_aux_usage usage) { return usage == ISL_AUX_USAGE_CCS_D || usage == ISL_AUX_USAGE_CCS_E || - usage == ISL_AUX_USAGE_GFX12_CCS_E || + usage == ISL_AUX_USAGE_FCV_CCS_E || usage == ISL_AUX_USAGE_MC || usage == ISL_AUX_USAGE_HIZ_CCS_WT || usage == ISL_AUX_USAGE_HIZ_CCS || @@ -2214,7 +2216,7 @@ static inline bool isl_aux_usage_has_ccs_e(enum isl_aux_usage usage) { return usage == ISL_AUX_USAGE_CCS_E || - usage == ISL_AUX_USAGE_GFX12_CCS_E; + usage == ISL_AUX_USAGE_FCV_CCS_E; } static inline bool @@ -2279,7 +2281,7 @@ isl_drm_modifier_get_default_aux_state(uint64_t modifier) return ISL_AUX_STATE_AUX_INVALID; assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || - mod_info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + mod_info->aux_usage == ISL_AUX_USAGE_FCV_CCS_E || mod_info->aux_usage == ISL_AUX_USAGE_MC); return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR : ISL_AUX_STATE_COMPRESSED_NO_CLEAR; diff --git a/src/intel/isl/isl_aux_info.c b/src/intel/isl/isl_aux_info.c index e013bfe4120..bfeb9e35ee2 100644 --- a/src/intel/isl/isl_aux_info.c +++ b/src/intel/isl/isl_aux_info.c @@ -92,7 +92,7 @@ static const struct aux_usage_info info[] = { AUX( COMPRESS, Y, Y, Y, x, MCS) AUX( COMPRESS, Y, Y, Y, x, MCS_CCS) AUX( COMPRESS, Y, Y, Y, Y, CCS_E) - AUX( COMPRESS_CLEAR, Y, Y, Y, Y, GFX12_CCS_E) + AUX( COMPRESS_CLEAR, Y, Y, Y, Y, FCV_CCS_E) AUX(RESOLVE_AMBIGUATE, x, Y, x, Y, CCS_D) AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC) AUX( COMPRESS, Y, x, x, Y, STC_CCS) diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index 23d2de0a9d4..5a193fdcc6e 100644 --- a/src/intel/isl/isl_drm.c +++ b/src/intel/isl/isl_drm.c @@ -104,7 +104,7 @@ isl_drm_modifier_info_list[] = { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS", .tiling = ISL_TILING_Y0, - .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, + .aux_usage = ISL_AUX_USAGE_FCV_CCS_E, .supports_clear_color = false, }, { @@ -118,7 +118,7 @@ isl_drm_modifier_info_list[] = { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC", .tiling = ISL_TILING_Y0, - .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, + .aux_usage = ISL_AUX_USAGE_FCV_CCS_E, .supports_clear_color = true, }, { @@ -130,7 +130,7 @@ isl_drm_modifier_info_list[] = { .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS", .tiling = ISL_TILING_4, - .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, + .aux_usage = ISL_AUX_USAGE_FCV_CCS_E, .supports_clear_color = false, }, { @@ -144,7 +144,7 @@ isl_drm_modifier_info_list[] = { .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC", .tiling = ISL_TILING_4, - .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E, + .aux_usage = ISL_AUX_USAGE_FCV_CCS_E, .supports_clear_color = true, }, { diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 6860c0552cb..f7fd331ea8f 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -71,7 +71,7 @@ static const uint32_t isl_encode_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_MC] = AUX_NONE, [ISL_AUX_USAGE_MCS] = AUX_CCS_E, - [ISL_AUX_USAGE_GFX12_CCS_E] = AUX_CCS_E, + [ISL_AUX_USAGE_FCV_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E, [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, @@ -587,7 +587,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, if (GFX_VER >= 12) { assert(info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_E || - info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + info->aux_usage == ISL_AUX_USAGE_FCV_CCS_E || info->aux_usage == ISL_AUX_USAGE_MC || info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || info->aux_usage == ISL_AUX_USAGE_MCS_CCS || diff --git a/src/intel/isl/tests/isl_aux_info_test.cpp b/src/intel/isl/tests/isl_aux_info_test.cpp index 503199bb26d..f0d4a3a8c3f 100644 --- a/src/intel/isl/tests/isl_aux_info_test.cpp +++ b/src/intel/isl/tests/isl_aux_info_test.cpp @@ -377,20 +377,20 @@ TEST(StateTransitionWrite, WritesCompress) { } TEST(StateTransitionWrite, WritesCompressClear) { - E(CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(PARTIAL_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(PARTIAL_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(COMPRESSED_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(COMPRESSED_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(COMPRESSED_NO_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(COMPRESSED_NO_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(RESOLVED, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(RESOLVED, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(PASS_THROUGH, GFX12_CCS_E, false, COMPRESSED_CLEAR); - E(PASS_THROUGH, GFX12_CCS_E, true, COMPRESSED_CLEAR); - E(AUX_INVALID, GFX12_CCS_E, false, ASSERT); - E(AUX_INVALID, GFX12_CCS_E, true, ASSERT); + E(CLEAR, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(CLEAR, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(PARTIAL_CLEAR, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(PARTIAL_CLEAR, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(COMPRESSED_CLEAR, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(COMPRESSED_CLEAR, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(COMPRESSED_NO_CLEAR, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(COMPRESSED_NO_CLEAR, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(RESOLVED, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(RESOLVED, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(PASS_THROUGH, FCV_CCS_E, false, COMPRESSED_CLEAR); + E(PASS_THROUGH, FCV_CCS_E, true, COMPRESSED_CLEAR); + E(AUX_INVALID, FCV_CCS_E, false, ASSERT); + E(AUX_INVALID, FCV_CCS_E, true, ASSERT); } TEST(StateTransitionWrite, WritesResolveAmbiguate) { diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 314c3174176..1ad9914d444 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -351,7 +351,7 @@ can_fast_clear_with_non_zero_color(const struct intel_device_info *devinfo, * - Texture view rendering (including blorp_copy calls) * - Images with multiple levels or array layers */ - if (image->planes[plane].aux_usage == ISL_AUX_USAGE_GFX12_CCS_E) + if (image->planes[plane].aux_usage == ISL_AUX_USAGE_FCV_CCS_E) return false; /* Non mutable image, we can fast clear with any color supported by HW. @@ -758,7 +758,7 @@ add_aux_surface_if_supported(struct anv_device *device, image->vk.usage, fmt_list)) { image->planes[plane].aux_usage = intel_needs_workaround(device->info, 1607794140) ? - ISL_AUX_USAGE_GFX12_CCS_E : + ISL_AUX_USAGE_FCV_CCS_E : ISL_AUX_USAGE_CCS_E; } else if (device->info->ver >= 12) { anv_perf_warn(VK_LOG_OBJS(&image->vk.base), @@ -1925,7 +1925,7 @@ VkResult anv_BindImageMemory2( image->planes[p].aux_usage = ISL_AUX_USAGE_HIZ; } else { assert(image->planes[p].aux_usage == ISL_AUX_USAGE_CCS_E || - image->planes[p].aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || + image->planes[p].aux_usage == ISL_AUX_USAGE_FCV_CCS_E || image->planes[p].aux_usage == ISL_AUX_USAGE_STC_CCS); image->planes[p].aux_usage = ISL_AUX_USAGE_NONE; } @@ -2167,7 +2167,7 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo, break; case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: case ISL_AUX_USAGE_STC_CCS: break; @@ -2201,7 +2201,7 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo, } case ISL_AUX_USAGE_CCS_E: - case ISL_AUX_USAGE_GFX12_CCS_E: + case ISL_AUX_USAGE_FCV_CCS_E: if (aux_supported) { assert(clear_supported); return ISL_AUX_STATE_COMPRESSED_CLEAR; @@ -2356,7 +2356,7 @@ anv_layout_to_fast_clear_type(const struct intel_device_info * const devinfo, return ANV_FAST_CLEAR_DEFAULT_VALUE; } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS || image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E || - image->planes[plane].aux_usage == ISL_AUX_USAGE_GFX12_CCS_E) { + image->planes[plane].aux_usage == ISL_AUX_USAGE_FCV_CCS_E) { if (devinfo->ver >= 11) { /* The image might not support non zero fast clears when mutable. */ if (!image->planes[plane].can_non_zero_fast_clear)