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asahi: drop unused patch index buffer lowering

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30382>
This commit is contained in:
Alyssa Rosenzweig 2024-07-17 13:50:35 -04:00 • committed by Marge Bot
parent 3992a54dcf
commit 0bd897989e
3 changed files with 9 additions and 20 deletions
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3
src/asahi/lib/agx_nir_lower_gs.h
View file

@ -24,8 +24,7 @@ struct nir_def *agx_load_per_vertex_input(struct nir_builder *b,
nir_intrinsic_instr *intr, nir_intrinsic_instr *intr,
struct nir_def *vertex); struct nir_def *vertex);
bool agx_nir_lower_index_buffer(struct nir_shader *s, unsigned index_size_B, bool agx_nir_lower_index_buffer(struct nir_shader *s, unsigned index_size_B);
bool patches);
bool agx_nir_lower_sw_vs_id(nir_shader *s); bool agx_nir_lower_sw_vs_id(nir_shader *s);

24
src/asahi/lib/agx_nir_lower_ia.c
View file

@ -19,29 +19,19 @@
* vertex shaders, as part of geometry/tessellation lowering. It does not apply * vertex shaders, as part of geometry/tessellation lowering. It does not apply
* the topology, which happens in the geometry shader. * the topology, which happens in the geometry shader.
*/ */
struct state {
unsigned index_size;
bool patches;
};
static nir_def * static nir_def *
load_vertex_id(nir_builder *b, struct state *state) load_vertex_id(nir_builder *b, unsigned index_size_B)
{ {
nir_def *id = nir_load_primitive_id(b); nir_def *id = nir_load_primitive_id(b);
if (state->patches) {
id = nir_iadd(b, nir_imul(b, id, nir_load_patch_vertices_in(b)),
nir_load_invocation_id(b));
}
/* If drawing with an index buffer, pull the vertex ID. Otherwise, the /* If drawing with an index buffer, pull the vertex ID. Otherwise, the
* vertex ID is just the index as-is. * vertex ID is just the index as-is.
*/ */
if (state->index_size) { if (index_size_B) {
nir_def *ia = nir_load_input_assembly_buffer_agx(b); nir_def *ia = nir_load_input_assembly_buffer_agx(b);
nir_def *index = nir_def *index =
libagx_load_index_buffer(b, ia, id, nir_imm_int(b, state->index_size)); libagx_load_index_buffer(b, ia, id, nir_imm_int(b, index_size_B));
id = nir_u2uN(b, index, id->bit_size); id = nir_u2uN(b, index, id->bit_size);
} }
@ -58,16 +48,16 @@ lower_vertex_id(nir_builder *b, nir_intrinsic_instr *intr, void *data)
if (intr->intrinsic != nir_intrinsic_load_vertex_id) if (intr->intrinsic != nir_intrinsic_load_vertex_id)
return false; return false;
unsigned *index_size_B = data;
b->cursor = nir_instr_remove(&intr->instr); b->cursor = nir_instr_remove(&intr->instr);
assert(intr->def.bit_size == 32); assert(intr->def.bit_size == 32);
nir_def_rewrite_uses(&intr->def, load_vertex_id(b, data)); nir_def_rewrite_uses(&intr->def, load_vertex_id(b, *index_size_B));
return true; return true;
} }
bool bool
agx_nir_lower_index_buffer(nir_shader *s, unsigned index_size_B, bool patches) agx_nir_lower_index_buffer(nir_shader *s, unsigned index_size_B)
{ {
return nir_shader_intrinsics_pass(s, lower_vertex_id, return nir_shader_intrinsics_pass(s, lower_vertex_id,
nir_metadata_control_flow, nir_metadata_control_flow, &index_size_B);
&(struct state){index_size_B, patches});
} }

2
src/asahi/lib/agx_nir_prolog_epilog.c
View file

@ -169,7 +169,7 @@ agx_nir_vs_prolog(nir_builder *b, const void *key_)
lower_vbo(b->shader, key->attribs, key->robustness); lower_vbo(b->shader, key->attribs, key->robustness);
if (!key->hw) { if (!key->hw) {
agx_nir_lower_index_buffer(b->shader, key->sw_index_size_B, false); agx_nir_lower_index_buffer(b->shader, key->sw_index_size_B);
agx_nir_lower_sw_vs_id(b->shader); agx_nir_lower_sw_vs_id(b->shader);
} }