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nir: Use SM5 properties to optimize shift(a@32, iand(31, b))

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This is a common pattern from HLSL->SPIRV translation
and supported in HW by all current NIR backends.

vkpipeline-db results anv (SKL):

    total instructions in shared programs: 6403130 -> 6402380 (-0.01%)
    instructions in affected programs: 204084 -> 203334 (-0.37%)
    helped: 208
    HURT: 0

    total cycles in shared programs: 1915629582 -> 1918198408 (0.13%)
    cycles in affected programs: 1158892682 -> 1161461508 (0.22%)
    helped: 107
    HURT: 86

shader-db results on i965 (KBL):

    total instructions in shared programs: 15284592 -> 15284568 (<.01%)
    instructions in affected programs: 81683 -> 81659 (-0.03%)
    helped: 24
    HURT: 0

    total cycles in shared programs: 375013622 -> 375013932 (<.01%)
    cycles in affected programs: 40169618 -> 40169928 (<.01%)
    helped: 13
    HURT: 9

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Daniel Schürmann 2019-02-22 22:05:07 +01:00 • committed by Jason Ekstrand
parent 0525bdc225
commit 0bd45f96b9
1 changed files with 5 additions and 0 deletions
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5
src/compiler/nir/nir_opt_algebraic.py
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@ -552,6 +552,11 @@ optimizations = [
(('ine', ('ineg', ('b2i', 'a@1')), -1), ('inot', a)),
(('iand', ('ineg', ('b2i', a)), 1.0), ('b2f', a)),
# SM5 32-bit shifts are defined to use the 5 least significant bits
(('ishl', 'a@32', ('iand', 31, b)), ('ishl', a, b)),
(('ishr', 'a@32', ('iand', 31, b)), ('ishr', a, b)),
(('ushr', 'a@32', ('iand', 31, b)), ('ushr', a, b)),
# Conversions
(('i2b32', ('b2i', 'a@32')), a),
(('f2i', ('ftrunc', a)), ('f2i', a)),