From 0b6e613de8d0c42d01a762fe1d37d77cfa8aeb47 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Mon, 22 Aug 2022 21:47:02 -0700 Subject: [PATCH] intel/compiler: Create and use struct for CS thread payload Move subgroup_id, that's only used by CS for verx10 < 125, as part of the payload too -- even though is not, strictly speaking. Note the thread execution of Task/Mesh is similar enough, so we make their common struct inherit from cs_thread_payload. Reviewed-by: Francisco Jerez Part-of: --- src/intel/compiler/brw_fs.cpp | 14 ++------- src/intel/compiler/brw_fs.h | 18 ++++++++++-- src/intel/compiler/brw_fs_nir.cpp | 9 ++---- src/intel/compiler/brw_fs_thread_payload.cpp | 31 ++++++++++++++++++++ 4 files changed, 50 insertions(+), 22 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index e4381fe7cce..8969e35ecd9 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1146,7 +1146,6 @@ fs_visitor::import_uniforms(fs_visitor *v) { this->push_constant_loc = v->push_constant_loc; this->uniforms = v->uniforms; - this->subgroup_id = v->subgroup_id; } void @@ -5852,16 +5851,6 @@ fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) con fprintf(file, "\n"); } -void -fs_visitor::setup_cs_payload() -{ - thread_payload &payload = this->payload(); - - assert(devinfo->ver >= 7); - /* TODO: Fill out uses_btd_stack_ids automatically */ - payload.num_regs = 1 + brw_cs_prog_data(prog_data)->uses_btd_stack_ids; -} - brw::register_pressure::register_pressure(const fs_visitor *v) { const fs_live_variables &live = v->live_analysis.require(); @@ -6802,8 +6791,9 @@ bool fs_visitor::run_cs(bool allow_spilling) { assert(gl_shader_stage_is_compute(stage)); + assert(devinfo->ver >= 7); - setup_cs_payload(); + payload_ = new cs_thread_payload(*this); if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) { /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */ diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 168f4c4895b..dd68b83025c 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -141,7 +141,16 @@ struct fs_thread_payload : public thread_payload { uint8_t local_invocation_id_reg[2]; }; -struct task_mesh_thread_payload : public thread_payload { +struct cs_thread_payload : public thread_payload { + cs_thread_payload(const fs_visitor &v); + + void load_subgroup_id(const brw::fs_builder &bld, fs_reg &dest) const; + +protected: + fs_reg subgroup_id_; +}; + +struct task_mesh_thread_payload : public cs_thread_payload { task_mesh_thread_payload(const fs_visitor &v); fs_reg extended_parameter_0; @@ -209,7 +218,6 @@ public: bool run_mesh(bool allow_spilling); void optimize(); void allocate_registers(bool allow_spilling); - void setup_cs_payload(); bool fixup_sends_duplicate_payload(); void fixup_3src_null_dest(); void emit_dummy_memory_fence_before_eot(); @@ -448,7 +456,6 @@ public: */ int *push_constant_loc; - fs_reg subgroup_id; fs_reg scratch_base; fs_reg frag_depth; fs_reg frag_stencil; @@ -497,6 +504,11 @@ public: return *static_cast(this->payload_); }; + cs_thread_payload &cs_payload() { + assert(gl_shader_stage_uses_workgroup(stage)); + return *static_cast(this->payload_); + } + task_mesh_thread_payload &task_mesh_payload() { assert(stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH); return *static_cast(this->payload_); diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9f4eda6ee0d..ac5e8774979 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -118,7 +118,7 @@ fs_visitor::nir_setup_uniforms() */ uint32_t *param = brw_stage_prog_data_add_params(prog_data, 1); *param = BRW_PARAM_BUILTIN_SUBGROUP_ID; - subgroup_id = fs_reg(UNIFORM, uniforms++, BRW_REGISTER_TYPE_UD); + uniforms++; } } @@ -3762,12 +3762,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld, break; case nir_intrinsic_load_subgroup_id: - if (devinfo->verx10 >= 125) - bld.AND(retype(dest, BRW_REGISTER_TYPE_UD), - retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), - brw_imm_ud(INTEL_MASK(7, 0))); - else - bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), subgroup_id); + cs_payload().load_subgroup_id(bld, dest); break; case nir_intrinsic_load_local_invocation_id: diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index 40fe9753abf..25b3a6c89d7 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -366,7 +366,37 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v, runtime_check_aads_emit); } +cs_thread_payload::cs_thread_payload(const fs_visitor &v) +{ + /* See nir_setup_uniforms for subgroup_id in earlier versions. */ + if (v.devinfo->verx10 >= 125) + subgroup_id_ = retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD); + + /* TODO: Fill out uses_btd_stack_ids automatically */ + num_regs = 1 + brw_cs_prog_data(v.prog_data)->uses_btd_stack_ids; +} + +void +cs_thread_payload::load_subgroup_id(const fs_builder &bld, + fs_reg &dest) const +{ + auto devinfo = bld.shader->devinfo; + dest = retype(dest, BRW_REGISTER_TYPE_UD); + + if (subgroup_id_.file != BAD_FILE) { + assert(devinfo->verx10 >= 125); + bld.AND(dest, subgroup_id_, brw_imm_ud(INTEL_MASK(7, 0))); + } else { + assert(devinfo->verx10 < 125); + assert(gl_shader_stage_is_compute(bld.shader->stage)); + int index = brw_get_subgroup_id_param_index(devinfo, + bld.shader->stage_prog_data); + bld.MOV(dest, fs_reg(UNIFORM, index, BRW_REGISTER_TYPE_UD)); + } +} + task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v) + : cs_thread_payload(v) { /* Task and Mesh Shader Payloads (SIMD8 and SIMD16) * @@ -388,6 +418,7 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v) */ unsigned r = 0; + assert(subgroup_id_.file != BAD_FILE); extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD); urb_output = retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD);