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intel/brw: Allow extra SWSB encodings for Xe2

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There are new combinations of ordered and unordered dependencies
available for the instructions to use, which among others include:

- combining FLOAT and INT pipe deps in SENDs;
- combining SRC mode deps in regular instructions for the inferred type.

This patch enables a couple of tests checking for the first case.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31375>
This commit is contained in:
Caio Oliveira 2024-09-24 21:25:42 -07:00 • committed by Marge Bot
parent 1b13eea642
commit 0b66cb1f82
2 changed files with 17 additions and 5 deletions
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16
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -987,15 +987,27 @@ namespace {
exec_all).pipe;
const tgl_sbid_mode unordered_mode =
baked_unordered_dependency_mode(devinfo, inst, deps, jp);
const tgl_pipe inferred_pipe = inferred_sync_pipe(devinfo, inst);
if (!has_ordered)
return false;
else if (!unordered_mode)
return true;
else
return ordered_pipe == inferred_sync_pipe(devinfo, inst) &&
else if (devinfo->ver < 20)
return ordered_pipe == inferred_pipe &&
unordered_mode == (is_unordered(devinfo, inst) ? TGL_SBID_SET :
TGL_SBID_DST);
else if (is_send(inst))
return unordered_mode == TGL_SBID_SET &&
(ordered_pipe == TGL_PIPE_FLOAT ||
ordered_pipe == TGL_PIPE_INT ||
ordered_pipe == TGL_PIPE_ALL);
else if (inst->opcode == BRW_OPCODE_DPAS)
return ordered_pipe == inferred_pipe;
else
return (unordered_mode == TGL_SBID_DST && ordered_pipe == inferred_pipe) ||
(unordered_mode == TGL_SBID_SRC && ordered_pipe == inferred_pipe) ||
(unordered_mode == TGL_SBID_DST && ordered_pipe == TGL_PIPE_ALL);
}
/** @} */

6
src/intel/compiler/test_fs_scoreboard.cpp
View file

@ -947,7 +947,7 @@ TEST_F(scoreboard_test, gitlab_issue_from_mr_29723)
EXPECT_EQ(instruction(block0, 1)->sched, regdist(TGL_PIPE_FLOAT, 1));
}
TEST_F(scoreboard_test, DISABLED_combine_regdist_float_and_int_with_sbid_set)
TEST_F(scoreboard_test, combine_regdist_float_and_int_with_sbid_set)
{
devinfo->ver = 20;
devinfo->verx10 = 200;
@ -982,7 +982,7 @@ TEST_F(scoreboard_test, DISABLED_combine_regdist_float_and_int_with_sbid_set)
EXPECT_EQ(instruction(block0, 2)->sched, expected);
}
TEST_F(scoreboard_test, DISABLED_combine_regdist_float_with_sbid_set)
TEST_F(scoreboard_test, combine_regdist_float_with_sbid_set)
{
devinfo->ver = 20;
devinfo->verx10 = 200;
@ -1017,7 +1017,7 @@ TEST_F(scoreboard_test, DISABLED_combine_regdist_float_with_sbid_set)
EXPECT_EQ(instruction(block0, 2)->sched, expected);
}
TEST_F(scoreboard_test, DISABLED_combine_regdist_int_with_sbid_set)
TEST_F(scoreboard_test, combine_regdist_int_with_sbid_set)
{
devinfo->ver = 20;
devinfo->verx10 = 200;