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i965g: adapt to stencil ref changes

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while there also potentially fix logic ops (were never enabled before)
This commit is contained in:
Roland Scheidegger 2010-02-11 18:16:52 +01:00
parent 388109c04d
commit 0b659dee69
3 changed files with 34 additions and 6 deletions
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25
src/gallium/drivers/i965/brw_cc.c
View file

@ -65,14 +65,33 @@ combine_cc3( struct brw_cc3 a, struct brw_cc3 b )
return ca.cc3;
}
static INLINE struct brw_cc1
combine_cc1( struct brw_cc1 a, struct brw_cc1 b )
{
union { struct brw_cc1 cc1; unsigned i; } ca, cb;
ca.cc1 = a;
cb.cc1 = b;
ca.i |= cb.i;
return ca.cc1;
}
static INLINE struct brw_cc2
combine_cc2( struct brw_cc2 a, struct brw_cc2 b )
{
union { struct brw_cc2 cc2; unsigned i; } ca, cb;
ca.cc2 = a;
cb.cc2 = b;
ca.i |= cb.i;
return ca.cc2;
}
static int prepare_cc_unit( struct brw_context *brw )
{
brw->cc.cc.cc0 = brw->curr.zstencil->cc0;
brw->cc.cc.cc1 = brw->curr.zstencil->cc1;
brw->cc.cc.cc2 = brw->curr.zstencil->cc2;
brw->cc.cc.cc1 = combine_cc1( brw->curr.zstencil->cc1, brw->curr.cc1_stencil_ref );
brw->cc.cc.cc2 = combine_cc2( brw->curr.zstencil->cc2, brw->curr.blend->cc2 );
brw->cc.cc.cc3 = combine_cc3( brw->curr.zstencil->cc3, brw->curr.blend->cc3 );
brw->cc.cc.cc5 = brw->curr.blend->cc5;
brw->cc.cc.cc6 = brw->curr.blend->cc6;
brw->cc.cc.cc7 = brw->curr.zstencil->cc7;

3
src/gallium/drivers/i965/brw_context.h
View file

@ -153,7 +153,6 @@ struct brw_blend_state {
struct brw_surf_ss0 ss0;
};
struct brw_rasterizer_state;
struct brw_immediate_data {
@ -560,12 +559,14 @@ struct brw_context
struct pipe_scissor_state scissor;
struct pipe_viewport_state viewport;
struct pipe_stencil_ref stencil_ref;
struct pipe_framebuffer_state fb;
struct pipe_clip_state ucp;
struct pipe_buffer *vertex_constants;
struct pipe_buffer *fragment_constants;
struct brw_blend_constant_color bcc;
struct brw_cc1 cc1_stencil_ref;
struct brw_polygon_stipple bps;
struct brw_cc_viewport ccv;

12
src/gallium/drivers/i965/brw_pipe_depth.c
View file

@ -72,7 +72,6 @@ static void create_bcc_state( struct brw_depth_stencil_state *zstencil,
translate_stencil_op(templ->stencil[0].zfail_op);
zstencil->cc0.stencil_pass_depth_pass_op =
translate_stencil_op(templ->stencil[0].zpass_op);
zstencil->cc1.stencil_ref = templ->stencil[0].ref_value;
zstencil->cc1.stencil_write_mask = templ->stencil[0].writemask;
zstencil->cc1.stencil_test_mask = templ->stencil[0].valuemask;
@ -86,7 +85,6 @@ static void create_bcc_state( struct brw_depth_stencil_state *zstencil,
translate_stencil_op(templ->stencil[1].zfail_op);
zstencil->cc0.bf_stencil_pass_depth_pass_op =
translate_stencil_op(templ->stencil[1].zpass_op);
zstencil->cc1.bf_stencil_ref = templ->stencil[1].ref_value;
zstencil->cc2.bf_stencil_write_mask = templ->stencil[1].writemask;
zstencil->cc2.bf_stencil_test_mask = templ->stencil[1].valuemask;
}
@ -159,9 +157,19 @@ static void brw_delete_depth_stencil_state(struct pipe_context *pipe,
FREE(cso);
}
static void brw_set_stencil_ref(struct pipe_context *pipe,
const struct pipe_stencil_ref *stencil_ref)
{
struct brw_context *brw = brw_context(pipe);
brw->curr.cc1_stencil_ref.stencil_ref = stencil_ref->ref_value[0];
brw->curr.cc1_stencil_ref.bf_stencil_ref = stencil_ref->ref_value[1];
brw->state.dirty.mesa |= PIPE_NEW_DEPTH_STENCIL_ALPHA;
}
void brw_pipe_depth_stencil_init( struct brw_context *brw )
{
brw->base.set_stencil_ref = brw_set_stencil_ref;
brw->base.create_depth_stencil_alpha_state = brw_create_depth_stencil_state;
brw->base.bind_depth_stencil_alpha_state = brw_bind_depth_stencil_state;
brw->base.delete_depth_stencil_alpha_state = brw_delete_depth_stencil_state;