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radv/nir: simplify lowering of query intrinsics

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32702>
This commit is contained in:
Samuel Pitoiset 2024-12-17 17:22:58 +01:00 • committed by Marge Bot
parent a7d32be1dd
commit 0b3e7ec36f
1 changed files with 17 additions and 19 deletions
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36
src/amd/vulkan/nir/radv_nir_lower_abi.c
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@ -378,30 +378,28 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
break;
}
case nir_intrinsic_atomic_add_gs_emit_prim_count_amd:
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa, nir_imm_int(b, RADV_SHADER_QUERY_GS_PRIM_EMIT_OFFSET),
nir_imm_int(b, 0x100));
break;
case nir_intrinsic_atomic_add_gen_prim_count_amd: {
uint32_t offset = stage == MESA_SHADER_MESH ? RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET
: RADV_SHADER_QUERY_PRIM_GEN_OFFSET(nir_intrinsic_stream_id(intrin));
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa, nir_imm_int(b, offset), nir_imm_int(b, 0x100));
break;
}
case nir_intrinsic_atomic_add_gen_prim_count_amd:
case nir_intrinsic_atomic_add_xfb_prim_count_amd:
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa,
nir_imm_int(b, RADV_SHADER_QUERY_PRIM_XFB_OFFSET(nir_intrinsic_stream_id(intrin))),
nir_imm_int(b, 0x100));
break;
case nir_intrinsic_atomic_add_shader_invocation_count_amd: {
uint32_t offset;
if (stage == MESA_SHADER_MESH) {
offset = RADV_SHADER_QUERY_MS_INVOCATION_OFFSET;
} else if (stage == MESA_SHADER_TASK) {
offset = RADV_SHADER_QUERY_TS_INVOCATION_OFFSET;
if (intrin->intrinsic == nir_intrinsic_atomic_add_gs_emit_prim_count_amd) {
offset = RADV_SHADER_QUERY_GS_PRIM_EMIT_OFFSET;
} else if (intrin->intrinsic == nir_intrinsic_atomic_add_gen_prim_count_amd) {
offset = stage == MESA_SHADER_MESH ? RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET
: RADV_SHADER_QUERY_PRIM_GEN_OFFSET(nir_intrinsic_stream_id(intrin));
} else if (intrin->intrinsic == nir_intrinsic_atomic_add_xfb_prim_count_amd) {
offset = RADV_SHADER_QUERY_PRIM_XFB_OFFSET(nir_intrinsic_stream_id(intrin));
} else {
offset = RADV_SHADER_QUERY_GS_INVOCATION_OFFSET;
assert(intrin->intrinsic == nir_intrinsic_atomic_add_shader_invocation_count_amd);
if (stage == MESA_SHADER_MESH) {
offset = RADV_SHADER_QUERY_MS_INVOCATION_OFFSET;
} else if (stage == MESA_SHADER_TASK) {
offset = RADV_SHADER_QUERY_TS_INVOCATION_OFFSET;
} else {
offset = RADV_SHADER_QUERY_GS_INVOCATION_OFFSET;
}
}
nir_gds_atomic_add_amd(b, 32, intrin->src[0].ssa, nir_imm_int(b, offset), nir_imm_int(b, 0x100));