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i965/fs: Move GL_CLAMP handling to coordinate setup.

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We should be able to merge self-move instruction into the MRF move
anyway, and this simplifies things for the next commit.

NOTE: This is a candidate for the 8.0 release branch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 07e621c523)
This commit is contained in:
Eric Anholt 2012-02-03 19:06:08 +01:00 • committed by Ian Romanick
parent 0d1049ff26
commit 0b2ffc647d
1 changed files with 21 additions and 29 deletions
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50
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
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@ -633,11 +633,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
if (ir->shadow_comparitor && ir->op != ir_txd) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV,
fs_reg(MRF, base_mrf + mlen + i), coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
coordinate.reg_offset++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
@ -665,10 +661,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
mlen++;
} else if (ir->op == ir_tex) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
coordinate.reg_offset++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
@ -726,12 +719,8 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF,
base_mrf + mlen + i * 2,
coordinate.type),
coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
coordinate);
coordinate.reg_offset++;
}
@ -838,12 +827,9 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
}
for (int i = 0; i < vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV,
fs_reg(MRF, base_mrf + mlen + i * reg_width,
coordinate.type),
coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV,
fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
coordinate);
coordinate.reg_offset++;
}
mlen += vector_elements * reg_width;
@ -988,10 +974,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
* [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
*/
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate);
coordinate.reg_offset++;
mlen += reg_width;
@ -1033,10 +1016,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
/* Set up the coordinate (except for cases where it was done above) */
if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
coordinate);
if (i < 3 && c->key.tex.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate);
coordinate.reg_offset++;
mlen += reg_width;
}
@ -1153,6 +1133,18 @@ fs_visitor::visit(ir_texture *ir)
emit(BRW_OPCODE_MUL, dst, src, scale_y);
}
if (ir->coordinate) {
for (int i = 0; i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
fs_reg chan = coordinate;
chan.reg_offset += i;
fs_inst *inst = emit(BRW_OPCODE_MOV, chan, chan);
inst->saturate = true;
}
}
}
/* Writemasking doesn't eliminate channels on SIMD8 texture
* samples, so don't worry about them.
*/