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r300: set proper texture row alignment for IGP chips

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Looks like r400 based IGP chips require 64 byte alignment
This commit is contained in:
Maciej Cencora 2009-05-02 17:27:03 +02:00 • committed by Alex Deucher
parent 55db6ce537
commit 0b22615c2c
4 changed files with 14 additions and 5 deletions
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5
src/mesa/drivers/dri/r300/r300_context.c
View file

@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
if (r300->radeon.radeonScreen->kernel_mm)
driInitExtensions(ctx, mm_extensions, GL_FALSE);
if (screen->chip_family == CHIP_FAMILY_RS600 || screen->chip_family == CHIP_FAMILY_RS690 ||
screen->chip_family == CHIP_FAMILY_RS740) {
r300->radeon.texture_row_align = 64;
}
r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
"def_max_anisotropy");

2
src/mesa/drivers/dri/radeon/radeon_common_context.c
View file

@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
radeon->texture_row_align = 32;
return GL_TRUE;
}

1
src/mesa/drivers/dri/radeon/radeon_common_context.h
View file

@ -421,6 +421,7 @@ struct radeon_context {
*/
int texture_depth;
float initialMaxAnisotropy;
uint32_t texture_row_align;
struct radeon_dma dma;
struct radeon_hw_state hw;

11
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
View file

@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
* \param curOffset points to the offset at which the image is to be stored
* and is updated by this function according to the size of the image.
*/
static void compute_tex_image_offset(radeon_mipmap_tree *mt,
static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
GLuint face, GLuint level, GLuint* curOffset)
{
radeon_mipmap_level *lvl = &mt->levels[level];
uint32_t row_align = rmesa->texture_row_align - 1;
/* Find image size in bytes */
if (mt->compressed) {
@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
} else {
lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
lvl->size = lvl->rowstride * lvl->height * lvl->depth;
}
assert(lvl->size > 0);
@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels)
return size;
}
static void calculate_miptree_layout(radeon_mipmap_tree *mt)
static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
GLuint curOffset;
GLuint numLevels;
@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt)
mt->levels[i].depth = minify(mt->depth0, i);
for(face = 0; face < mt->faces; face++)
compute_tex_image_offset(mt, face, i, &curOffset);
compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
}
/* Note the required size in memory */
@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
mt->tilebits = tilebits;
mt->compressed = compressed;
calculate_miptree_layout(mt);
calculate_miptree_layout(rmesa, mt);
mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
0, mt->totalsize, 1024,