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i965/blorp: Prepare sampling for gen9

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v2 (Ken): Added switch cases for gen8/9 in texel_fetch(). These
          were wrongly introduced in blit-enabling patch.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2016-04-01 11:21:03 +03:00
parent 328ab6c268
commit 0ad83d222b
1 changed files with 14 additions and 2 deletions
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16
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
View file

@ -1629,12 +1629,19 @@ brw_blorp_blit_program::texel_fetch(struct brw_reg dst)
SAMPLER_MESSAGE_ARG_U_INT,
SAMPLER_MESSAGE_ARG_V_INT
};
static const sampler_message_arg gen9_ld_args[3] = {
SAMPLER_MESSAGE_ARG_U_INT,
SAMPLER_MESSAGE_ARG_V_INT,
SAMPLER_MESSAGE_ARG_ZERO_INT /* LOD */
};
switch (brw->gen) {
case 6:
texture_lookup(dst, SHADER_OPCODE_TXF, gen6_args, s_is_zero ? 2 : 5);
break;
case 7:
case 8:
case 9:
switch (key->tex_layout) {
case INTEL_MSAA_LAYOUT_IMS:
/* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
@ -1657,8 +1664,13 @@ brw_blorp_blit_program::texel_fetch(struct brw_reg dst)
break;
case INTEL_MSAA_LAYOUT_NONE:
assert(s_is_zero);
texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args,
ARRAY_SIZE(gen7_ld_args));
if (brw->gen < 9) {
texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args,
ARRAY_SIZE(gen7_ld_args));
} else {
texture_lookup(dst, SHADER_OPCODE_TXF, gen9_ld_args,
ARRAY_SIZE(gen9_ld_args));
}
break;
}
break;