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intel: Fix and use HIZ_CCS write through mode

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Write through to the CCS if the surface is used as a texture and can be
sampled by the HW with CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Nanley Chery 2019-08-21 10:57:29 -07:00
parent fee4dbcb4d
commit 0aa308f420
2 changed files with 7 additions and 0 deletions
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1
src/intel/genxml/gen12.xml
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@ -1893,6 +1893,7 @@
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Hierarchical Depth Buffer Write Thru Enable" start="52" end="52" type="bool"/>
<field name="Tiled Resource Mode" start="54" end="55" type="uint">
<value name="NONE" value="0"/>
<value name="TILEYF" value="1"/>

6
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -192,6 +192,12 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
hiz.SurfaceBaseAddress = info->hiz_address;
hiz.MOCS = info->mocs;
hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
#if GEN_GEN >= 12
hiz.HierarchicalDepthBufferWriteThruEnable =
isl_surf_supports_hiz_ccs_wt(dev->info, info->depth_surf,
info->hiz_usage);
#endif
#if GEN_GEN >= 8
/* From the SKL PRM Vol2a:
*