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aco/spill: don't prefer to spill phis at merge blocks

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Totals from 44 (0.06% of 79242) affected shaders: (GFX11)

Instrs: 165578 -> 165545 (-0.02%); split: -0.08%, +0.06%
CodeSize: 833528 -> 832988 (-0.06%); split: -0.11%, +0.04%
SpillSGPRs: 346 -> 329 (-4.91%)
Latency: 1176341 -> 1176231 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 235771 -> 235761 (-0.00%); split: -0.01%, +0.01%
SClause: 3287 -> 3289 (+0.06%); split: -0.21%, +0.27%
Copies: 16290 -> 16299 (+0.06%); split: -0.62%, +0.68%
Branches: 3633 -> 3641 (+0.22%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27774>
This commit is contained in:
Daniel Schürmann 2024-02-19 14:19:52 +01:00 • committed by Marge Bot
parent d234f789b5
commit 09c5414760
1 changed files with 10 additions and 7 deletions
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17
src/amd/compiler/aco_spill.cpp
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@ -693,11 +693,14 @@ init_live_in_vars(spill_ctx& ctx, Block* block, unsigned block_idx)
Block::edge_vec& preds =
phi->opcode == aco_opcode::p_phi ? block->logical_preds : block->linear_preds;
bool is_all_spilled = true;
bool is_partial_spill = false;
for (unsigned i = 0; i < phi->operands.size(); i++) {
if (phi->operands[i].isUndefined())
continue;
is_all_spilled &= phi->operands[i].isTemp() &&
ctx.spills_exit[preds[i]].count(phi->operands[i].getTemp());
bool spilled = phi->operands[i].isTemp() &&
ctx.spills_exit[preds[i]].count(phi->operands[i].getTemp());
is_all_spilled &= spilled;
is_partial_spill |= spilled;
}
if (is_all_spilled) {
@ -706,7 +709,7 @@ init_live_in_vars(spill_ctx& ctx, Block* block, unsigned block_idx)
spilled_registers += phi->definitions[0].getTemp();
} else {
/* Phis might increase the register pressure. */
partial_spills[phi->definitions[0].getTemp()] = true;
partial_spills[phi->definitions[0].getTemp()] = is_partial_spill;
}
}
@ -718,19 +721,19 @@ init_live_in_vars(spill_ctx& ctx, Block* block, unsigned block_idx)
assert(!partial_spills.empty());
std::map<Temp, bool>::iterator it = partial_spills.begin();
Temp to_spill = Temp();
bool is_spilled_or_phi = false;
bool is_partial_spill = false;
unsigned distance = 0;
RegType type = reg_pressure.vgpr > ctx.target_pressure.vgpr ? RegType::vgpr : RegType::sgpr;
while (it != partial_spills.end()) {
assert(!ctx.spills_entry[block_idx].count(it->first));
if (it->first.type() == type && ((it->second && !is_spilled_or_phi) ||
(it->second == is_spilled_or_phi &&
if (it->first.type() == type && ((it->second && !is_partial_spill) ||
(it->second == is_partial_spill &&
next_use_distances.at(it->first).second > distance))) {
distance = next_use_distances.at(it->first).second;
to_spill = it->first;
is_spilled_or_phi = it->second;
is_partial_spill = it->second;
}
++it;
}