From 09b43966bacdc23099d609048ecdf38e6abe3b64 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 23 Apr 2026 19:42:09 -0700 Subject: [PATCH] brw: Lower all phis to scalar The next commit will cause some very specific phis to not be lowered to scalar, and that's the reason the callback is used instead of nir_lower_all_phis_to_scalar. It's worth noting that the comment in nir_lower_phis_to_scalar.c specifically calls out Deus Ex as the reason some phis should not be lowered. At least on current BRW, zero shaders from Deus Ex trace were affected for spills or fills on any Intel platform. shader-db: All Intel platforms had similar results. (Lunar Lake shown) total instructions in shared programs: 17050005 -> 17051449 (<.01%) instructions in affected programs: 41032 -> 42476 (3.52%) helped: 29 / HURT: 159 total cycles in shared programs: 876411976 -> 876433702 (<.01%) cycles in affected programs: 1455550 -> 1477276 (1.49%) helped: 40 / HURT: 150 fossil-db: All Intel platforms had similar results. (Lunar Lake shown) Totals: Instrs: 916599633 -> 916694854 (+0.01%); split: -0.00%, +0.01% CodeSize: 14705971792 -> 14708302384 (+0.02%); split: -0.00%, +0.02% Send messages: 40870114 -> 40870113 (-0.00%) Cycle count: 102360965889 -> 102364169753 (+0.00%); split: -0.00%, +0.01% Spill count: 3460669 -> 3460240 (-0.01%) Fill count: 4988325 -> 4987891 (-0.01%) Max live registers: 192914542 -> 192918153 (+0.00%); split: -0.00%, +0.00% Max dispatch width: 48848112 -> 48848128 (+0.00%) Non SSA regs after NIR: 141633613 -> 141671589 (+0.03%); split: -0.00%, +0.03% Totals from 5713 (0.28% of 2010434) affected shaders: Instrs: 5215921 -> 5311142 (+1.83%); split: -0.09%, +1.91% CodeSize: 88940784 -> 91271376 (+2.62%); split: -0.20%, +2.82% Send messages: 284751 -> 284750 (-0.00%) Cycle count: 275671864 -> 278875728 (+1.16%); split: -0.74%, +1.90% Spill count: 857 -> 428 (-50.06%) Fill count: 845 -> 411 (-51.36%) Max live registers: 667776 -> 671387 (+0.54%); split: -0.86%, +1.40% Max dispatch width: 160416 -> 160432 (+0.01%) Non SSA regs after NIR: 1127904 -> 1165880 (+3.37%); split: -0.10%, +3.47% Reviewed-by: Kenneth Graunke Tested-by: Matt Corallo Part-of: --- src/intel/compiler/brw/brw_nir.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c index e38b513a4cd..d9189315a67 100644 --- a/src/intel/compiler/brw/brw_nir.c +++ b/src/intel/compiler/brw/brw_nir.c @@ -1698,6 +1698,12 @@ brw_nir_tag_speculative_access(nir_shader *nir) nir_metadata_all, NULL); } +static uint8_t +brw_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_) +{ + return 1; +} + #define OPT BRW_NIR_PASS #define LOOP_OPT BRW_NIR_LOOP_PASS #define LOOP_OPT_NOT_IDEMPOTENT BRW_NIR_LOOP_PASS_NOT_IDEMPOTENT @@ -1735,7 +1741,7 @@ brw_nir_optimize(brw_pass_tracker *pt) LOOP_OPT(nir_opt_copy_prop); - LOOP_OPT(nir_lower_phis_to_scalar, NULL, NULL); + LOOP_OPT(nir_lower_phis_to_scalar, brw_nir_lower_phis_to_scalar_cb, NULL); LOOP_OPT(nir_opt_copy_prop); LOOP_OPT(nir_opt_dce);