From 095e4f5f1bbf1c7cfd6fd3a34993347bfe03dbf4 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Tue, 2 Jun 2026 13:56:34 -0700 Subject: [PATCH] brw: control cache_mode through bypass_{l1,l3} variables This change splits the algorithm in two steps: first we have the logical decision of which caches to bypass based on the needs of the send operation, and then we have the code that picks the caching modes based on which caches to bypass. This should make it significantly easier for us to add new workarounds without the risk of breaking existing cases. Reviewed-by: Sagar Ghuge Signed-off-by: Paulo Zanoni Part-of: --- .../compiler/brw/brw_lower_logical_sends.cpp | 38 ++++++++++--------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/src/intel/compiler/brw/brw_lower_logical_sends.cpp b/src/intel/compiler/brw/brw_lower_logical_sends.cpp index 7a2fb24b115..9444028a090 100644 --- a/src/intel/compiler/brw/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw/brw_lower_logical_sends.cpp @@ -1302,31 +1302,35 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_mem_inst *mem) * residencyNonResidentStrict guarantees. Due to the above, we need to make * these operations uncached. */ - unsigned atomic_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); - unsigned store_cache_mode = LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS); - unsigned load_cache_mode = LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS); - + bool bypass_l1 = false; + bool bypass_l3 = false; if (devinfo->ver >= 20 && mesa_shader_stage_is_rt(bld.shader->stage) && send->sfid == GEN_SFID_TGM) { /* Disable LSC data port L1 cache scheme for the TGM load/store for RT * shaders (see HSD 18038444588). */ - store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); - load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3C); + bypass_l1 = true; } else if (volatile_access) { - if (devinfo->ver >= 20) { - /* Xe2 has a better L3 that can deal with null tiles. */ - store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); - load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3C); - } else { - /* On older platforms, all caches have to be bypassed. */ - store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3UC); - load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3UC); - } + /* Xe2 has a better L3 that can deal with null tiles. On older + * platforms, all caches have to be bypassed. + */ + bypass_l1 = true; + if (devinfo->ver < 20) + bypass_l3 = true; } else if (coherent_access) { /* Skip L1 for coherent accesses. */ - store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); - load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3C); + bypass_l1 = true; + } + + unsigned atomic_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); + unsigned store_cache_mode = LSC_CACHE(devinfo, STORE, L1STATE_L3MOCS); + unsigned load_cache_mode = LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS); + if (bypass_l3) { + store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3UC); + load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3UC); + } else if (bypass_l1) { + store_cache_mode = LSC_CACHE(devinfo, STORE, L1UC_L3WB); + load_cache_mode = LSC_CACHE(devinfo, LOAD, L1UC_L3C); } const unsigned cache_mode =