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turnip: share code between 3D blit/clear path and tu_pipeline
Instead of filling out registers manually, fill out ir3 structs and re-use code from tu_pipeline. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5426>
This commit is contained in:
Jonathan Marek
Marge Bot
parent
13525a9c70
commit
093c413722
4 changed files with 106 additions and 133 deletions
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@ -485,6 +485,59 @@ r2d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
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static void
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r3d_pipeline(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_rts)
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{
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struct ir3_shader dummy_shader = {};
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struct ir3_shader_variant vs = {
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.type = MESA_SHADER_VERTEX,
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.instrlen = 1,
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.constlen = 2,
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.info.max_reg = 1,
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.inputs_count = 1,
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.inputs[0] = {
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.slot = SYSTEM_VALUE_VERTEX_ID,
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.regid = regid(0, 3),
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.sysval = true,
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},
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.outputs_count = blit ? 2 : 1,
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.outputs[0] = {
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.slot = VARYING_SLOT_POS,
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.regid = regid(0, 0),
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},
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.outputs[1] = {
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.slot = VARYING_SLOT_VAR0,
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.regid = regid(1, 0),
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},
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.shader = &dummy_shader,
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};
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struct ir3_shader_variant fs = {
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.type = MESA_SHADER_FRAGMENT,
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.instrlen = 1, /* max of 9 instructions with num_rts = 8 */
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.constlen = num_rts,
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.info.max_reg = MAX2(num_rts, 1) - 1,
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.total_in = blit ? 2 : 0,
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.num_samp = blit ? 1 : 0,
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.inputs_count = blit ? 2 : 0,
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.inputs[0] = {
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.slot = VARYING_SLOT_VAR0,
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.inloc = 0,
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.compmask = 3,
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.bary = true,
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},
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.inputs[1] = {
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.slot = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
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.regid = regid(0, 0),
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.sysval = 1,
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},
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.num_sampler_prefetch = blit ? 1 : 0,
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.sampler_prefetch[0] = {
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.src = 0,
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.wrmask = 0xf,
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.cmd = 4,
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},
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.shader = &dummy_shader,
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};
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static const instr_t vs_code[] = {
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/* r0.xyz = r0.w ? c1.xyz : c0.xyz
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* r1.xy = r0.w ? c1.zw : c0.zw
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@ -509,85 +562,6 @@ r3d_pipeline(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t nu
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#define FS_OFFSET (16 * sizeof(instr_t))
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STATIC_ASSERT(sizeof(vs_code) <= FS_OFFSET);
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/* vs inputs: only vtx id in r0.w */
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tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 7);
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tu_cs_emit(cs, 0x00000000);
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tu_cs_emit(cs, 0xfcfcfc00 | A6XX_VFD_CONTROL_1_REGID4VTX(3));
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tu_cs_emit(cs, 0x0000fcfc);
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tu_cs_emit(cs, 0xfcfcfcfc);
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tu_cs_emit(cs, 0x000000fc);
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tu_cs_emit(cs, 0x0000fcfc);
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tu_cs_emit(cs, 0x00000000);
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/* vs outputs: position in r0.xyzw, blit coords in r1.xy */
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
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tu_cs_emit(cs, blit ? 0xffffffcf : 0xffffffff);
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tu_cs_emit(cs, 0xffffffff);
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tu_cs_emit(cs, 0xffffffff);
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tu_cs_emit(cs, 0xffffffff);
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tu_cs_emit_regs(cs, A6XX_SP_VS_OUT_REG(0,
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.a_regid = 0, .a_compmask = 0xf,
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.b_regid = 4, .b_compmask = 0x3));
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tu_cs_emit_regs(cs, A6XX_SP_VS_VPC_DST_REG(0, .outloc0 = 0, .outloc1 = 4));
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
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tu_cs_emit(cs, 0xff00ff00 |
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COND(blit, A6XX_VPC_CNTL_0_VARYING) |
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A6XX_VPC_CNTL_0_NUMNONPOSVAR(blit ? 8 : 0));
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tu_cs_emit_regs(cs, A6XX_VPC_PACK(
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.positionloc = 0,
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.psizeloc = 0xff,
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.stride_in_vpc = blit ? 6 : 4));
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tu_cs_emit_regs(cs, A6XX_SP_PRIMITIVE_CNTL(.vsout = blit ? 2 : 1));
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tu_cs_emit_regs(cs,
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A6XX_PC_PRIMITIVE_CNTL_0(),
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A6XX_PC_PRIMITIVE_CNTL_1(.stride_in_vpc = blit ? 6 : 4));
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
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tu_cs_emit(cs, blit ? 0xe000 : 0); // I think this can just be 0
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for (uint32_t i = 1; i < 8; i++)
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
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for (uint32_t i = 0; i < 8; i++)
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tu_cs_emit(cs, 0x99999999);
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/* fs inputs: none, prefetch in blit case */
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + blit);
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tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(blit) |
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A6XX_SP_FS_PREFETCH_CNTL_UNK4(0xfc) |
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0x7000);
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if (blit) {
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tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(4) |
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A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(0) |
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A6XX_SP_FS_PREFETCH_CMD_TEX_ID(0) |
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A6XX_SP_FS_PREFETCH_CMD_DST(0) |
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A6XX_SP_FS_PREFETCH_CMD_WRMASK(0xf) |
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A6XX_SP_FS_PREFETCH_CMD_CMD(0x4));
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}
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tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
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tu_cs_emit(cs, 0x3); // XXX blob uses 3 in blit path
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tu_cs_emit(cs, 0xfcfcfcfc);
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tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(blit ? 0 : 0xfc) |
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A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(0xfc) |
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0xfc00fc00);
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tu_cs_emit(cs, 0xfcfcfcfc);
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tu_cs_emit(cs, 0xfcfc);
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tu_cs_emit_regs(cs, A6XX_HLSQ_UNKNOWN_B980(blit ? 3 : 1));
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tu_cs_emit_regs(cs, A6XX_GRAS_CNTL(.varying = blit));
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tu_cs_emit_regs(cs,
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A6XX_RB_RENDER_CONTROL0(.varying = blit, .unk10 = blit),
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A6XX_RB_RENDER_CONTROL1());
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tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_CNTL());
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tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8101());
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tu_cs_emit_regs(cs, A6XX_GRAS_SAMPLE_CNTL());
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/* shaders */
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struct ts_cs_memory shaders = { };
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VkResult result = tu_cs_alloc(&cmd->sub_cs, 2, 16 * sizeof(instr_t), &shaders);
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@ -595,67 +569,45 @@ r3d_pipeline(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t nu
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memcpy(shaders.map, vs_code, sizeof(vs_code));
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instr_t *fs = (instr_t*) ((uint8_t*) shaders.map + FS_OFFSET);
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instr_t *fs_code = (instr_t*) ((uint8_t*) shaders.map + FS_OFFSET);
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for (uint32_t i = 0; i < num_rts; i++) {
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/* (rpt3)mov.s32s32 r0.x, (r)c[i].x */
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fs[i] = (instr_t) { .cat1 = { .opc_cat = 1, .src_type = TYPE_S32, .dst_type = TYPE_S32,
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.repeat = 3, .dst = i * 4, .src_c = 1, .src_r = 1, .src = i * 4 } };
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*fs_code++ = (instr_t) { .cat1 = {
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.opc_cat = 1, .src_type = TYPE_S32, .dst_type = TYPE_S32,
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.repeat = 3, .dst = i * 4, .src_c = 1, .src_r = 1, .src = i * 4
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} };
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}
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fs[num_rts] = (instr_t) { .cat0 = { .opc = OPC_END } };
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/* " bary.f (ei)r63.x, 0, r0.x" note the blob doesn't have this in its
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* blit path (its not clear what allows it to not have it)
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*/
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if (blit) {
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*fs_code++ = (instr_t) { .cat2 = {
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.opc_cat = 2, .opc = OPC_BARY_F & 63, .ei = 1, .full = 1,
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.dst = regid(63, 0), .src1_im = 1
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} };
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}
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*fs_code++ = (instr_t) { .cat0 = { .opc = OPC_END } };
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/* note: assumed <= 16 instructions (MAX_RTS is 8) */
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tu_cs_emit_regs(cs, A6XX_HLSQ_UPDATE_CNTL(0x7ffff));
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tu_cs_emit_regs(cs,
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A6XX_HLSQ_VS_CNTL(.constlen = 8, .enabled = true),
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A6XX_HLSQ_HS_CNTL(),
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A6XX_HLSQ_DS_CNTL(),
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A6XX_HLSQ_GS_CNTL());
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tu_cs_emit_regs(cs, A6XX_HLSQ_FS_CNTL(.constlen = 4 * num_rts, .enabled = true));
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tu_cs_emit_regs(cs,
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A6XX_SP_VS_CONFIG(.enabled = true),
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A6XX_SP_VS_INSTRLEN(1));
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tu_cs_emit_regs(cs, A6XX_SP_HS_CONFIG());
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tu_cs_emit_regs(cs, A6XX_SP_DS_CONFIG());
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tu_cs_emit_regs(cs, A6XX_SP_GS_CONFIG());
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tu_cs_emit_regs(cs,
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A6XX_SP_FS_CONFIG(.enabled = true, .ntex = blit, .nsamp = blit),
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A6XX_SP_FS_INSTRLEN(1));
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tu6_emit_xs_config(cs, MESA_SHADER_VERTEX, &vs, shaders.iova);
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tu6_emit_xs_config(cs, MESA_SHADER_TESS_CTRL, NULL, 0);
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tu6_emit_xs_config(cs, MESA_SHADER_TESS_EVAL, NULL, 0);
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tu6_emit_xs_config(cs, MESA_SHADER_GEOMETRY, NULL, 0);
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tu6_emit_xs_config(cs, MESA_SHADER_FRAGMENT, &fs, shaders.iova + FS_OFFSET);
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tu_cs_emit_regs(cs, A6XX_SP_VS_CTRL_REG0(
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.threadsize = FOUR_QUADS,
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.fullregfootprint = 2,
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.mergedregs = true));
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tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0(
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.varying = blit,
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.threadsize = FOUR_QUADS,
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/* could this be 0 in !blit && !num_rts case ? */
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.fullregfootprint = MAX2(1, num_rts),
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.mergedregs = true)); /* note: tu_pipeline also sets 0x1000000 bit */
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tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0());
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tu_cs_emit_regs(cs, A6XX_VFD_CONTROL_0());
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tu_cs_emit_regs(cs, A6XX_SP_IBO_COUNT(0));
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tu6_emit_vpc(cs, &vs, NULL, &fs, NULL);
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tu_cs_emit_pkt7(cs, CP_LOAD_STATE6_GEOM, 3);
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(1));
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tu_cs_emit_qw(cs, shaders.iova);
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/* REPL_MODE for varying with RECTLIST (2 vertices only) */
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tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE(0, 0));
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tu_cs_emit_regs(cs, A6XX_VPC_VARYING_PS_REPL_MODE(0, 2 << 2 | 1 << 0));
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OBJ_START_LO, 2);
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tu_cs_emit_qw(cs, shaders.iova);
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tu_cs_emit_pkt7(cs, CP_LOAD_STATE6_FRAG, 3);
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(1));
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tu_cs_emit_qw(cs, shaders.iova + FS_OFFSET);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OBJ_START_LO, 2);
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tu_cs_emit_qw(cs, shaders.iova + FS_OFFSET);
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tu6_emit_fs_inputs(cs, &fs);
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tu_cs_emit_regs(cs,
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A6XX_GRAS_CL_CNTL(
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@ -628,7 +628,7 @@ tu6_blend_op(VkBlendOp op)
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}
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}
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static void
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void
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tu6_emit_xs_config(struct tu_cs *cs,
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gl_shader_stage stage, /* xs->type, but xs may be NULL */
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const struct ir3_shader_variant *xs,
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@ -731,7 +731,9 @@ tu6_emit_xs_config(struct tu_cs *cs,
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COND(xs->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
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COND(xs->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
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COND(xs->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
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COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO));
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COND(xs->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO) |
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A6XX_SP_VS_CONFIG_NTEX(xs->num_samp) |
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A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
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tu_cs_emit(cs, xs->instrlen);
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tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
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@ -1003,7 +1005,7 @@ gl_primitive_to_tess(uint16_t primitive) {
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}
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}
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static void
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void
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tu6_emit_vpc(struct tu_cs *cs,
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const struct ir3_shader_variant *vs,
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const struct ir3_shader_variant *gs,
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@ -1268,7 +1270,7 @@ tu6_emit_vpc_varying_modes(struct tu_cs *cs,
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tu_cs_emit_array(cs, ps_repl_modes, 8);
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}
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static void
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void
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tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
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{
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uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
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@ -1445,6 +1445,22 @@ void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_
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void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
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void
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tu6_emit_xs_config(struct tu_cs *cs,
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gl_shader_stage stage,
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const struct ir3_shader_variant *xs,
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uint64_t binary_iova);
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void
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tu6_emit_vpc(struct tu_cs *cs,
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const struct ir3_shader_variant *vs,
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const struct ir3_shader_variant *gs,
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const struct ir3_shader_variant *fs,
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struct tu_streamout_state *tf);
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void
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tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);
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struct tu_image_view;
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void
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@ -741,6 +741,9 @@ tu_compile_shader_variant(struct ir3_shader *shader,
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if (ret)
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return NULL;
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/* num_samp should be 0 for bindless, but we use it with blit shader */
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variant->num_samp = 0;
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/* when assemble fails, we rely on tu_shader_destroy to clean up the
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* variant
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*/
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