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radeonsi: tune primitive binning for small chips

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same as PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
This commit is contained in:
Marek Olšák 2020-03-10 20:46:16 -04:00 • committed by Marge Bot
parent 629b6ddd71
commit 09295e95eb
1 changed files with 9 additions and 3 deletions
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12
src/gallium/drivers/radeonsi/si_state_binning.c
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@ -485,7 +485,8 @@ void si_emit_dpbb_state(struct si_context *sctx)
G_02880C_DEPTH_BEFORE_SHADER(db_shader_control);
/* Disable DPBB when it's believed to be inefficient. */
if (ps_can_kill &&
if (sscreen->info.num_render_backends > 4 &&
ps_can_kill &&
db_can_reject_z_trivially &&
sctx->framebuffer.state.zsbuf &&
dsa->db_can_write) {
@ -546,8 +547,13 @@ void si_emit_dpbb_state(struct si_context *sctx)
/* Tuned for Raven. Vega might need different values. */
if (sscreen->info.has_dedicated_vram) {
context_states_per_bin = 1;
persistent_states_per_bin = 1;
if (sscreen->info.num_render_backends > 4) {
context_states_per_bin = 1;
persistent_states_per_bin = 1;
} else {
context_states_per_bin = 3;
persistent_states_per_bin = 8;
}
} else {
/* This is a workaround for:
* https://bugs.freedesktop.org/show_bug.cgi?id=110214