diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index f88bfe39ba8..2de5614bc18 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -3428,6 +3428,7 @@ nir_tex_instr_need_sampler(const nir_tex_instr *instr)
    case nir_texop_fragment_mask_fetch_amd:
    case nir_texop_fragment_fetch_amd:
    case nir_texop_resinfo_intel:
+   case nir_texop_sparse_residency_txf_intel:
       return false;
    default:
       return true;
@@ -3475,6 +3476,8 @@ nir_tex_instr_result_size(const nir_tex_instr *instr)
    case nir_texop_fragment_mask_fetch_amd:
    case nir_texop_image_min_lod_agx:
    case nir_texop_has_custom_border_color_agx:
+   case nir_texop_sparse_residency_intel:
+   case nir_texop_sparse_residency_txf_intel:
       return 1;
 
    case nir_texop_descriptor_amd:
@@ -3526,6 +3529,8 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
    case nir_texop_tex_type_nv:
    case nir_texop_sample_pos_nv:
    case nir_texop_resinfo_intel:
+   case nir_texop_sparse_residency_intel:
+   case nir_texop_sparse_residency_txf_intel:
       return true;
    case nir_texop_tex:
    case nir_texop_txb:
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 0678290e461..df0a9c529cb 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2517,6 +2517,11 @@ typedef enum nir_texop {
    nir_texop_block_match_ssd_qcom,
    /** txs in .xyz and query_levels in .w */
    nir_texop_resinfo_intel,
+
+   /** Returns red data and a sparse residency code for sampling ops */
+   nir_texop_sparse_residency_intel,
+   /** Returns red data and a sparse residency code for texel fetches */
+   nir_texop_sparse_residency_txf_intel,
 } nir_texop;
 
 /** Represents a texture instruction */
diff --git a/src/compiler/nir/nir_builder.c b/src/compiler/nir/nir_builder.c
index 98eadbd7ce0..3c6be2d513e 100644
--- a/src/compiler/nir/nir_builder.c
+++ b/src/compiler/nir/nir_builder.c
@@ -311,6 +311,8 @@ nir_build_tex_struct(nir_builder *build, nir_texop op, struct nir_tex_builder f)
    case nir_texop_fragment_mask_fetch_amd:
    case nir_texop_descriptor_amd:
    case nir_texop_resinfo_intel:
+   case nir_texop_sparse_residency_intel:
+   case nir_texop_sparse_residency_txf_intel:
       tex->dest_type = nir_type_int32;
       break;
    case nir_texop_lod:
diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c
index d51cd55c87a..3414bfa9e4b 100644
--- a/src/compiler/nir/nir_divergence_analysis.c
+++ b/src/compiler/nir/nir_divergence_analysis.c
@@ -1074,6 +1074,10 @@ visit_tex(nir_tex_instr *instr, struct divergence_state *state)
    if (instr->def.divergent)
       return false;
 
+   if (instr->op == nir_texop_sparse_residency_intel ||
+       instr->op == nir_texop_sparse_residency_txf_intel)
+      return true;
+
    bool is_divergent = false;
 
    for (unsigned i = 0; i < instr->num_srcs; i++) {
diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index b1227cfa028..c22f2f16e1c 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -1996,6 +1996,12 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
    case nir_texop_resinfo_intel:
       fprintf(fp, "resinfo_intel ");
       break;
+   case nir_texop_sparse_residency_intel:
+      fprintf(fp, "sparse_residency_intel ");
+      break;
+   case nir_texop_sparse_residency_txf_intel:
+      fprintf(fp, "sparse_residency_txf_intel ");
+      break;
    default:
       UNREACHABLE("Invalid texture operation");
       break;
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 3a3dacd0922..6b9f0866171 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -1040,7 +1040,9 @@ validate_tex_instr(nir_tex_instr *instr, validate_state *state)
 
       case nir_tex_src_ddx:
       case nir_tex_src_ddy:
-         validate_assert(state, instr->op == nir_texop_txd);
+         validate_assert(state,
+                         instr->op == nir_texop_txd ||
+                            instr->op == nir_texop_sparse_residency_intel);
          break;
 
       case nir_tex_src_texture_deref:
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index f47305189dd..fea0580ee9f 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3720,7 +3720,9 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
       vtn_fail("unexpected nir_texop_*_nv");
       break;
    case nir_texop_resinfo_intel:
-      vtn_fail("unexpected nir_texop_resinfo_intel");
+   case nir_texop_sparse_residency_intel:
+   case nir_texop_sparse_residency_txf_intel:
+      vtn_fail("unexpected internal tex op");
       break;
    }
 
diff --git a/src/intel/compiler/brw/brw_sampler.c b/src/intel/compiler/brw/brw_sampler.c
index 309a2702122..e126804bc1b 100644
--- a/src/intel/compiler/brw/brw_sampler.c
+++ b/src/intel/compiler/brw/brw_sampler.c
@@ -800,7 +800,8 @@ brw_get_sampler_opcode_from_tex(const struct intel_device_info *devinfo,
       tex->op == nir_texop_txf ||
       tex->op == nir_texop_txf_ms ||
       tex->op == nir_texop_txf_ms_fb ||
-      tex->op == nir_texop_txf_ms_mcs_intel;
+      tex->op == nir_texop_txf_ms_mcs_intel ||
+      tex->op == nir_texop_sparse_residency_txf_intel;
 
    const bool is_gather = tex->op == nir_texop_tg4;