diff --git a/src/intel/compiler/brw/tests/gen12/swsb.asm b/src/intel/compiler/brw/tests/gen12/swsb.asm index 7c813356cf3..30aa1ce106b 100644 --- a/src/intel/compiler/brw/tests/gen12/swsb.asm +++ b/src/intel/compiler/brw/tests/gen12/swsb.asm @@ -4,23 +4,23 @@ add(16) g122<1>F g98<8,8,1>F (abs)g102<8,8,1>F { align1 1H @3 shl(8) g75<1>D g122<8,8,1>D 0x00000002UD { align1 1Q @4 }; sel.l(4) g90.4<1>D g90.3<0,1,0>D g90.4<4,4,1>D { align1 WE_all 1N @5 }; and(16) g58<1>UD g16<8,8,1>UD g56<8,8,1>UD { align1 1H @6 }; -or.nz.f0.0(16) null<1>UD g105<8,8,1>UD g103<8,8,1>UD { align1 1H @7 }; +or.nz.f0.0(16) nullUD g105<8,8,1>UD g103<8,8,1>UD { align1 1H @7 }; -math cos(16) g17<1>F g15<8,8,1>F null<8,8,1>F { align1 1H @1 $0 }; -math exp(16) g1<1>F g29<8,8,1>F null<8,8,1>F { align1 1H @5 $2 }; -math sqrt(8) g9<1>HF g6<8,8,1>HF null<8,8,1>F { align1 1Q @1 $3 }; +math cos(16) g17<1>F g15<8,8,1>F nullUD { align1 1H @1 $0 }; +math exp(16) g1<1>F g29<8,8,1>F nullUD { align1 1H @5 $2 }; +math sqrt(8) g9<1>HF g6<8,8,1>HF nullUD { align1 1Q @1 $3 }; math intdiv(8) g103<1>D g101<8,8,1>D g35<8,8,1>D { align1 1Q @4 $4 }; math intmod(8) g101<1>D g97<8,8,1>D g76<8,8,1>D { align1 2Q @2 $5 }; -math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 2H @2 $6 }; -math log(16) g102<1>F g100<8,8,1>F null<8,8,1>F { align1 2H @1 $7 }; -math rsq(16) g76<1>F g74<8,8,1>F null<8,8,1>F { align1 1H @7 $8 }; -math sin(16) g123<1>F g121<8,8,1>F null<8,8,1>F { align1 1H @4 $9 }; -math sqrt(16) g43<1>F g47<8,8,1>F null<8,8,1>F { align1 2H @7 $10 }; -math cos(8) g103<1>HF g98<8,8,1>HF null<8,8,1>F { align1 1Q @3 $11 }; -math exp(8) g54<1>HF g52<8,8,1>HF null<8,8,1>F { align1 1Q @1 $12 }; +math inv(16) g10<1>F g8<8,8,1>F nullUD { align1 2H @2 $6 }; +math log(16) g102<1>F g100<8,8,1>F nullUD { align1 2H @1 $7 }; +math rsq(16) g76<1>F g74<8,8,1>F nullUD { align1 1H @7 $8 }; +math sin(16) g123<1>F g121<8,8,1>F nullUD { align1 1H @4 $9 }; +math sqrt(16) g43<1>F g47<8,8,1>F nullUD { align1 2H @7 $10 }; +math cos(8) g103<1>HF g98<8,8,1>HF nullUD { align1 1Q @3 $11 }; +math exp(8) g54<1>HF g52<8,8,1>HF nullUD { align1 1Q @1 $12 }; math intdiv(8) g35<1>D g31<8,8,1>D g33<8,8,1>D { align1 4Q @2 $13 }; math intmod(8) g101<1>D g97<8,8,1>D g99<8,8,1>D { align1 2Q @4 $14 }; -math inv(8) g102<1>HF g92<8,8,1>HF null<8,8,1>F { align1 1Q @6 $15 }; +math inv(8) g102<1>HF g92<8,8,1>HF nullUD { align1 1Q @6 $15 }; sel.ge(16) g7<1>UW g7<16,16,1>UW g89<16,8,2>UW { align1 1H @7 $0.dst }; mov(16) a0<1>UW 0x03e0UW { align1 WE_all 1H @3 $1.dst }; diff --git a/src/intel/compiler/brw/tests/gen12/swsb.expected b/src/intel/compiler/brw/tests/gen12/swsb.expected index 223c3fecdd9..b8cbccd8326 100644 --- a/src/intel/compiler/brw/tests/gen12/swsb.expected +++ b/src/intel/compiler/brw/tests/gen12/swsb.expected @@ -5,21 +5,21 @@ 62 05 02 80 60 06 85 5a 64 5a 00 56 85 5a 34 00 65 06 04 00 20 02 05 3a 05 10 46 02 05 38 46 00 66 07 04 00 20 02 01 00 05 69 46 22 05 67 46 00 -38 90 04 00 a0 0a 05 11 05 0f 46 7a 01 00 46 00 -38 d2 04 00 a0 0a 05 01 05 1d 46 3a 01 00 46 00 -38 93 03 00 90 09 05 09 05 06 46 4a 01 00 46 00 +38 90 04 00 a0 0a 05 11 05 0f 46 72 00 00 00 00 +38 d2 04 00 a0 0a 05 01 05 1d 46 32 00 00 00 00 +38 93 03 00 90 09 05 09 05 06 46 42 00 00 00 00 38 c4 03 00 60 06 05 67 05 65 46 c6 05 23 46 00 38 a5 13 00 60 06 05 65 05 61 46 d6 05 4c 46 00 -38 a6 24 00 a0 0a 05 0a 05 08 46 1a 01 00 46 00 -38 97 24 00 a0 0a 05 66 05 64 46 2a 01 00 46 00 -38 f8 04 00 a0 0a 05 4c 05 4a 46 5a 01 00 46 00 -38 c9 04 00 a0 0a 05 7b 05 79 46 6a 01 00 46 00 -38 fa 24 00 a0 0a 05 2b 05 2f 46 4a 01 00 46 00 -38 bb 03 00 90 09 05 67 05 62 46 7a 01 00 46 00 -38 9c 03 00 90 09 05 36 05 34 46 3a 01 00 46 00 +38 a6 24 00 a0 0a 05 0a 05 08 46 12 00 00 00 00 +38 97 24 00 a0 0a 05 66 05 64 46 22 00 00 00 00 +38 f8 04 00 a0 0a 05 4c 05 4a 46 52 00 00 00 00 +38 c9 04 00 a0 0a 05 7b 05 79 46 62 00 00 00 00 +38 fa 24 00 a0 0a 05 2b 05 2f 46 42 00 00 00 00 +38 bb 03 00 90 09 05 67 05 62 46 72 00 00 00 00 +38 9c 03 00 90 09 05 36 05 34 46 32 00 00 00 00 38 ad 33 00 60 06 05 23 05 1f 46 c6 05 21 46 00 38 ce 13 00 60 06 05 65 05 61 46 d6 05 63 46 00 -38 ef 03 00 90 09 05 66 05 5c 46 1a 01 00 46 00 +38 ef 03 00 90 09 05 66 05 5c 46 12 00 00 00 00 62 f0 04 00 10 01 05 07 05 07 58 41 06 59 56 00 61 b1 04 80 10 41 01 10 00 00 00 00 e0 03 e0 03 40 b2 04 00 60 86 05 64 05 66 46 06 be f7 ff ff diff --git a/src/intel/compiler/brw/tests/gen12/sync.asm b/src/intel/compiler/brw/tests/gen12/sync.asm index a47c5dec28c..bbd7f14b985 100644 --- a/src/intel/compiler/brw/tests/gen12/sync.asm +++ b/src/intel/compiler/brw/tests/gen12/sync.asm @@ -1,33 +1,33 @@ -sync nop(16) null<0,1,0>UB { align1 WE_all 1H @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @7 }; -sync nop(32) null<0,1,0>UB { align1 WE_all @1 }; -sync nop(8) null<0,1,0>UB { align1 WE_all 1Q @1 }; -sync allwr(16) null<0,1,0>UB { align1 1H }; -sync allwr(8) null<0,1,0>UB { align1 1Q }; +sync nop(16) nullUD { align1 WE_all 1H @1 }; +sync nop(1) nullUD { align1 WE_all 1N @1 }; +sync nop(1) nullUD { align1 WE_all 1N @2 }; +sync nop(1) nullUD { align1 WE_all 1N @3 }; +sync nop(1) nullUD { align1 WE_all 1N @4 }; +sync nop(1) nullUD { align1 WE_all 1N @5 }; +sync nop(1) nullUD { align1 WE_all 1N @6 }; +sync nop(1) nullUD { align1 WE_all 1N @7 }; +sync nop(1) nullUD { align1 WE_all 3N @1 }; +sync nop(1) nullUD { align1 WE_all 3N @2 }; +sync nop(1) nullUD { align1 WE_all 3N @3 }; +sync nop(1) nullUD { align1 WE_all 3N @4 }; +sync nop(1) nullUD { align1 WE_all 3N @5 }; +sync nop(1) nullUD { align1 WE_all 3N @6 }; +sync nop(1) nullUD { align1 WE_all 3N @7 }; +sync nop(1) nullUD { align1 WE_all 5N @1 }; +sync nop(1) nullUD { align1 WE_all 5N @2 }; +sync nop(1) nullUD { align1 WE_all 5N @3 }; +sync nop(1) nullUD { align1 WE_all 5N @4 }; +sync nop(1) nullUD { align1 WE_all 5N @5 }; +sync nop(1) nullUD { align1 WE_all 5N @6 }; +sync nop(1) nullUD { align1 WE_all 5N @7 }; +sync nop(1) nullUD { align1 WE_all 7N @1 }; +sync nop(1) nullUD { align1 WE_all 7N @2 }; +sync nop(1) nullUD { align1 WE_all 7N @3 }; +sync nop(1) nullUD { align1 WE_all 7N @4 }; +sync nop(1) nullUD { align1 WE_all 7N @5 }; +sync nop(1) nullUD { align1 WE_all 7N @6 }; +sync nop(1) nullUD { align1 WE_all 7N @7 }; +sync nop(32) nullUD { align1 WE_all @1 }; +sync nop(8) nullUD { align1 WE_all 1Q @1 }; +sync allwr(16) nullUD { align1 1H }; +sync allwr(8) nullUD { align1 1Q }; diff --git a/src/intel/compiler/brw/tests/gen12/sync.expected b/src/intel/compiler/brw/tests/gen12/sync.expected index 2e98e4ab791..2dfa36cbc94 100644 --- a/src/intel/compiler/brw/tests/gen12/sync.expected +++ b/src/intel/compiler/brw/tests/gen12/sync.expected @@ -1,33 +1,33 @@ -01 01 04 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 05 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 03 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 00 04 00 00 00 00 00 00 00 00 30 00 00 00 00 -01 00 03 00 00 00 00 00 00 00 00 30 00 00 00 00 +01 01 04 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 02 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 03 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 04 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 05 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 06 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 07 00 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 02 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 03 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 04 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 05 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 06 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 07 10 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 02 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 03 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 04 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 05 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 06 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 07 20 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 02 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 03 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 04 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 05 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 06 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 07 30 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 05 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 01 03 80 00 02 00 00 00 00 00 00 00 00 00 00 +01 00 04 00 00 02 00 00 00 00 00 30 00 00 00 00 +01 00 03 00 00 02 00 00 00 00 00 30 00 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/add.asm b/src/intel/compiler/brw/tests/gen9/add.asm index 5d751c29ab0..63baf2cbd0b 100644 --- a/src/intel/compiler/brw/tests/gen9/add.asm +++ b/src/intel/compiler/brw/tests/gen9/add.asm @@ -26,8 +26,8 @@ add(16) g11<1>UD g9<8,8,1>D 0x00000001UD { align1 1H }; add.sat(16) g126<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; add.sat(8) g124<1>F g17<8,8,1>D 1D { align1 1Q }; add(16) g114<1>D g118<8,8,1>D g116<8,8,1>D { align1 2H }; -add.z.f0.0(16) null<1>D g120<8,8,1>D 1D { align1 1H }; -add.z.f0.0(16) null<1>D g116<8,8,1>D 1D { align1 2H }; +add.z.f0.0(16) nullUD g120<8,8,1>D 1D { align1 1H }; +add.z.f0.0(16) nullUD g116<8,8,1>D 1D { align1 2H }; add.z.f0.0(8) g3<1>D g5<8,8,1>D g4<8,8,1>D { align1 1Q }; add(16) g20<1>UD g17<8,8,1>UD 1D { align1 1H }; add(8) g7<1>F -g6<4>.xyxyF g6<4>.zwzwF { align16 1Q }; diff --git a/src/intel/compiler/brw/tests/gen9/add.expected b/src/intel/compiler/brw/tests/gen9/add.expected index 438b6f14325..3e81e471659 100644 --- a/src/intel/compiler/brw/tests/gen9/add.expected +++ b/src/intel/compiler/brw/tests/gen9/add.expected @@ -26,8 +26,8 @@ 40 00 80 80 e8 3a c0 2f 40 00 00 3a 50 00 00 00 40 00 60 80 e8 0a 80 2f 20 02 8d 0e 01 00 00 00 40 20 80 00 28 0a 40 2e c0 0e 8d 0a 80 0e 8d 00 -40 00 80 01 20 0a 00 20 00 0f 8d 0e 01 00 00 00 -40 20 80 01 20 0a 00 20 80 0e 8d 0e 01 00 00 00 +40 00 80 01 00 0a 00 20 00 0f 8d 0e 01 00 00 00 +40 20 80 01 00 0a 00 20 80 0e 8d 0e 01 00 00 00 40 00 60 01 28 0a 60 20 a0 00 8d 0a 80 00 8d 00 40 00 80 00 08 02 80 22 20 02 8d 0e 01 00 00 00 40 01 60 00 e8 3a ef 20 c4 40 64 3a ce 00 6e 00 diff --git a/src/intel/compiler/brw/tests/gen9/and.asm b/src/intel/compiler/brw/tests/gen9/and.asm index 2f5d123fc84..130ca374c4e 100644 --- a/src/intel/compiler/brw/tests/gen9/and.asm +++ b/src/intel/compiler/brw/tests/gen9/and.asm @@ -3,8 +3,8 @@ and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H }; and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q }; and(16) g18<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H }; and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N }; -and.nz.f0.0(8) null<1>UD g36<8,8,1>UD g37<8,8,1>UD { align1 1Q }; -and.nz.f0.0(16) null<1>UD g70<8,8,1>UD g72<8,8,1>UD { align1 1H }; +and.nz.f0.0(8) nullUD g36<8,8,1>UD g37<8,8,1>UD { align1 1Q }; +and.nz.f0.0(16) nullUD g70<8,8,1>UD g72<8,8,1>UD { align1 1H }; and.z.f0.0(16) g21<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1H }; and(8) g61<1>UD g79<8,8,1>UD g32.1<8,4,2>UD { align1 2Q }; and(8) g96<1>D ~g94<8,8,1>D ~g95<8,8,1>D { align1 1Q }; @@ -12,15 +12,15 @@ and(16) g24<1>D ~g20<8,8,1>D ~g22<8,8,1>D { align1 1H }; and(1) a0<1>UD g4<0,1,0>UD 0x000000ffUD { align1 WE_all 1N }; and(16) g118<1>UD g114<8,8,1>UD 0x0000003fUD { align1 2H }; and(1) g4<1>UD g20<0,1,0>UD 0x000000ffUD { align1 WE_all 3N }; -and.z.f0.0(8) null<1>D g13<8,8,1>UD 0x0000001fUD { align1 1Q }; +and.z.f0.0(8) nullUD g13<8,8,1>UD 0x0000001fUD { align1 1Q }; and(8) g21<1>UD g15<8,8,1>UD 0x00000003UD { align1 WE_all 1Q }; -and.z.f0.0(8) null<1>UD g20<8,8,1>UD 0x00000001UD { align1 1Q }; -and.z.f0.0(16) null<1>UD g45<8,8,1>UD 0x00000001UD { align1 1H }; +and.z.f0.0(8) nullUD g20<8,8,1>UD 0x00000001UD { align1 1Q }; +and.z.f0.0(16) nullUD g45<8,8,1>UD 0x00000001UD { align1 1H }; and(8) g4<1>UW g3<8,8,1>UW 0xfffcUW { align1 1Q }; and(16) g13<1>UW g19<16,8,2>UW 0xfffcUW { align1 1H }; -and.nz.f0.0(8) null<1>UD ~g2.2<0,1,0>D g9<8,8,1>UD { align1 1Q }; +and.nz.f0.0(8) nullUD ~g2.2<0,1,0>D g9<8,8,1>UD { align1 1Q }; and(8) g18<1>UD ~g2.2<0,1,0>D g7<8,8,1>UD { align1 1Q }; -and.nz.f0.0(16) null<1>UD ~g2.2<0,1,0>D g14<8,8,1>UD { align1 1H }; +and.nz.f0.0(16) nullUD ~g2.2<0,1,0>D g14<8,8,1>UD { align1 1H }; and(16) g30<1>UD ~g2.2<0,1,0>D g10<8,8,1>UD { align1 1H }; and.nz.f0.0(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; and.nz.f0.0(16) g16<1>UD g14<8,8,1>UD 0x00000001UD { align1 1H }; diff --git a/src/intel/compiler/brw/tests/gen9/and.expected b/src/intel/compiler/brw/tests/gen9/and.expected index 4f2b62ecd1a..8f3dda23dc3 100644 --- a/src/intel/compiler/brw/tests/gen9/and.expected +++ b/src/intel/compiler/brw/tests/gen9/and.expected @@ -12,7 +12,7 @@ 05 00 00 00 04 02 00 22 80 00 00 06 ff 00 00 00 05 20 80 00 08 02 c0 2e 40 0e 8d 06 3f 00 00 00 05 10 00 00 0c 02 80 20 80 02 00 06 ff 00 00 00 -05 00 60 01 20 02 00 20 a0 01 8d 06 1f 00 00 00 +05 00 60 01 00 02 00 20 a0 01 8d 06 1f 00 00 00 05 00 60 00 0c 02 a0 22 e0 01 8d 06 03 00 00 00 05 00 60 01 00 02 00 20 80 02 8d 06 01 00 00 00 05 00 80 01 00 02 00 20 a0 05 8d 06 01 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/asr.asm b/src/intel/compiler/brw/tests/gen9/asr.asm index 9beabc9cc8b..9c4b5035c0c 100644 --- a/src/intel/compiler/brw/tests/gen9/asr.asm +++ b/src/intel/compiler/brw/tests/gen9/asr.asm @@ -1,6 +1,6 @@ asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q }; asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H }; -asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q }; -asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H }; +asr.nz.f0.0(8) nullUD -g0<0,1,0>W 15D { align1 1Q }; +asr.nz.f0.0(16) nullUD -g0<0,1,0>W 15D { align1 1H }; asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q }; asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H }; diff --git a/src/intel/compiler/brw/tests/gen9/asr.expected b/src/intel/compiler/brw/tests/gen9/asr.expected index f1832cd80d7..b384fe6232f 100644 --- a/src/intel/compiler/brw/tests/gen9/asr.expected +++ b/src/intel/compiler/brw/tests/gen9/asr.expected @@ -1,6 +1,6 @@ 0c 00 60 00 28 0a 60 22 e0 00 8d 06 01 00 00 00 0c 00 80 00 28 0a 80 22 5c 00 00 06 1f 00 00 00 -0c 00 60 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 -0c 00 80 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 +0c 00 60 02 00 1a 00 20 00 40 00 0e 0f 00 00 00 +0c 00 80 02 00 1a 00 20 00 40 00 0e 0f 00 00 00 0c 00 60 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 0c 00 80 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/cmp.asm b/src/intel/compiler/brw/tests/gen9/cmp.asm index 669224dcd0d..71df55c6550 100644 --- a/src/intel/compiler/brw/tests/gen9/cmp.asm +++ b/src/intel/compiler/brw/tests/gen9/cmp.asm @@ -1,7 +1,7 @@ -cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q }; +cmp.z.f0.0(8) nullUD g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q }; cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q }; cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q }; -cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q }; +cmp.nz.f0.0(8) nullUD g7<8,8,1>D 0D { align1 1Q }; cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q }; cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H }; cmp.l.f0.0(16) g28<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; @@ -9,96 +9,96 @@ cmp.ge.f0.0(16) g30<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q }; cmp.z.f0.0(8) g86<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q }; cmp.le.f0.0(8) g108<1>D g106<8,8,1>D 0D { align1 1Q }; -cmp.nz.f0.0(8) null<1>DF g6.2<0,1,0>DF g66<4,4,1>DF { align1 1Q }; +cmp.nz.f0.0(8) null<2>UD g6.2<0,1,0>DF g66<4,4,1>DF { align1 1Q }; cmp.l.f0.0(8) g5<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; cmp.ge.f0.0(8) g18<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; cmp.z.f0.0(8) g34<1>DF (abs)g106<4,4,1>DF g52<4,4,1>DF { align1 2Q }; cmp.le.f0.0(16) g35<1>D g21<8,8,1>D 0D { align1 1H }; -cmp.nz.f0.0(8) null<1>DF g106<4,4,1>DF g50<4,4,1>DF { align1 2Q }; +cmp.nz.f0.0(8) null<2>UD g106<4,4,1>DF g50<4,4,1>DF { align1 2Q }; cmp.nz.f0.0(8) g113<1>DF g3.1<0,1,0>DF g59<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(8) null<1>UD g12<8,8,1>UD 0x00000004UD { align1 1Q }; +cmp.l.f0.0(8) nullUD g12<8,8,1>UD 0x00000004UD { align1 1Q }; cmp.l.f0.0(8) g53<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; cmp.ge.f0.0(8) g55<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; cmp.ge.f0.0(8) g15<1>D (abs)g12<8,8,1>D 1D { align1 1Q }; -cmp.l.f0.0(8) null<1>D g6<0,1,0>D 2D { align1 1Q }; -(+f0.1) cmp.z.f0.1(8) null<1>D g8<8,8,1>D 0D { align1 1Q }; +cmp.l.f0.0(8) nullUD g6<0,1,0>D 2D { align1 1Q }; +(+f0.1) cmp.z.f0.1(8) nullUD g8<8,8,1>D 0D { align1 1Q }; cmp.nz.f0.0(16) g11<1>D g9<8,8,1>D 3D { align1 1H }; -(+f0.1) cmp.z.f0.1(16) null<1>D g11<8,8,1>D 0D { align1 1H }; -cmp.z.f0.0(8) null<1>D g22<8,8,1>D 1D { align1 1Q }; -cmp.z.f0.0(16) null<1>D g47<8,8,1>D 1D { align1 1H }; +(+f0.1) cmp.z.f0.1(16) nullUD g11<8,8,1>D 0D { align1 1H }; +cmp.z.f0.0(8) nullUD g22<8,8,1>D 1D { align1 1Q }; +cmp.z.f0.0(16) nullUD g47<8,8,1>D 1D { align1 1H }; cmp.ge.f0.0(8) g30<1>UD g29<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; cmp.l.f0.0(8) g31<1>UD g29<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; cmp.ge.f0.0(16) g50<1>UD g48<8,8,1>UD g7.7<0,1,0>UD { align1 1H }; cmp.l.f0.0(16) g52<1>UD g48<8,8,1>UD g7.3<0,1,0>UD { align1 1H }; cmp.nz.f0.0(16) g9<1>F g2.5<0,1,0>F g1.1<0,1,0>F { align1 1H }; -cmp.ge.f0.0(8) null<1>D g38<8,8,1>D 32D { align1 1Q }; -cmp.ge.f0.0(8) null<1>DF g21<4,4,1>DF g13<4,4,1>DF { align1 1Q }; +cmp.ge.f0.0(8) nullUD g38<8,8,1>D 32D { align1 1Q }; +cmp.ge.f0.0(8) null<2>UD g21<4,4,1>DF g13<4,4,1>DF { align1 1Q }; cmp.ge.f0.0(16) g3<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; cmp.l.f0.0(16) g5<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; cmp.z.f0.0(8) g25<1>F g4.3<0,1,0>F g4.1<0,1,0>F { align1 1Q }; cmp.l.f0.0(8) g33<1>D g5<0,1,0>D 1D { align1 1Q }; cmp.l.f0.0(8) g43<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; cmp.ge.f0.0(8) g46<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(16) null<1>D g6<0,1,0>D 1D { align1 1H }; +cmp.l.f0.0(16) nullUD g6<0,1,0>D 1D { align1 1H }; cmp.z.f0.0(16) g62<1>F g12<8,8,1>F g6.3<0,1,0>F { align1 1H }; -cmp.nz.f0.0(8) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.nz.f0.0(16) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1H }; -cmp.ge.f0.0(16) null<1>UD g46<8,8,1>UD 0x00000040UD { align1 1H }; -cmp.z.f0.0(16) null<1>F g14<8,8,1>F g6.1<0,1,0>F { align1 1H }; -cmp.nz.f0.0(16) null<1>D g6<0,1,0>D 0D { align1 1H }; -cmp.l.f0.0(16) null<1>UD g39<8,8,1>UD 0x00000004UD { align1 1H }; -cmp.le.f0.0(8) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; -cmp.le.f0.0(16) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; +cmp.nz.f0.0(8) nullUD g2<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.nz.f0.0(16) nullUD g2<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.ge.f0.0(16) nullUD g46<8,8,1>UD 0x00000040UD { align1 1H }; +cmp.z.f0.0(16) nullUD g14<8,8,1>F g6.1<0,1,0>F { align1 1H }; +cmp.nz.f0.0(16) nullUD g6<0,1,0>D 0D { align1 1H }; +cmp.l.f0.0(16) nullUD g39<8,8,1>UD 0x00000004UD { align1 1H }; +cmp.le.f0.0(8) nullUD g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; +cmp.le.f0.0(16) nullUD g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; cmp.le.f0.0(8) g20<1>F g5.3<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.ge.f0.0(8) null<1>F (abs)g26<8,8,1>F 0x5d5e0b6bF /* 1e+18F */ { align1 1Q }; +cmp.ge.f0.0(8) nullUD (abs)g26<8,8,1>F 0x5d5e0b6bF /* 1e+18F */ { align1 1Q }; cmp.g.f0.0(8) g80<1>F (abs)g44<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; -cmp.ge.f0.0(16) null<1>D g67<8,8,1>D 32D { align1 1H }; -cmp.g.f0.0(8) null<1>F g124<8,8,1>F 0x0F /* 0F */ { align1 1Q }; +cmp.ge.f0.0(16) nullUD g67<8,8,1>D 32D { align1 1H }; +cmp.g.f0.0(8) nullUD g124<8,8,1>F 0x0F /* 0F */ { align1 1Q }; cmp.z.f0.0(8) g4<1>F g13<8,4,2>F g2.5<0,1,0>F { align1 2Q }; -cmp.g.f0.0(16) null<1>F g120<8,8,1>F 0x0F /* 0F */ { align1 1H }; +cmp.g.f0.0(16) nullUD g120<8,8,1>F 0x0F /* 0F */ { align1 1H }; cmp.g.f0.0(16) g2<1>F (abs)g17<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; -cmp.l.f0.0(8) null<1>DF (abs)g5<0,1,0>DF g20<4,4,1>DF { align1 1Q }; +cmp.l.f0.0(8) null<2>UD (abs)g5<0,1,0>DF g20<4,4,1>DF { align1 1Q }; cmp.nz.f0.0(8) g29<1>D g22.1<8,4,2>D g3.2<0,1,0>D { align1 2Q }; -cmp.l.f0.0(8) null<1>DF g11<4,4,1>DF g8<4,4,1>DF { align1 2Q }; +cmp.l.f0.0(8) null<2>UD g11<4,4,1>DF g8<4,4,1>DF { align1 2Q }; cmp.nz.f0.0(8) g73<1>F g6.1<0,1,0>F g14<8,4,2>F { align1 2Q }; cmp.g.f0.0(8) g7<1>D g2<0,1,0>D 0D { align1 1Q }; -cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; -cmp.le.f0.0(8) null<1>D g2<8,8,1>D 50D { align1 1Q }; -cmp.le.f0.0(16) null<1>D g2<8,8,1>D 50D { align1 1H }; -cmp.ge.f0.0(16) null<1>F g35<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; +cmp.l.f0.0(8) nullUD g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; +cmp.l.f0.0(16) nullUD g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; +cmp.le.f0.0(8) nullUD g2<8,8,1>D 50D { align1 1Q }; +cmp.le.f0.0(16) nullUD g2<8,8,1>D 50D { align1 1H }; +cmp.ge.f0.0(16) nullUD g35<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; cmp.le.f0.0(8) g4<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; cmp.g.f0.0(8) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; cmp.le.f0.0(16) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; cmp.g.f0.0(16) g7<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; cmp.le.f0.0(16) g121<1>F g27<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 1H }; cmp.z.f0.0(8) g5<1>D g14<8,4,2>D g3.1<0,1,0>D { align1 2Q }; -cmp.g.f0.0(8) null<1>D g5.2<0,1,0>D 31D { align1 1Q }; -cmp.g.f0.0(8) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1Q }; -(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1Q }; -(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1H }; -cmp.z.f0.0(16) null<1>D g1<8,8,1>D 1024D { align1 2H }; -cmp.l.f0.0(16) null<1>D g118<8,8,1>D 32D { align1 2H }; -cmp.nz.f0.0(8) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1Q }; -cmp.nz.f0.0(16) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1H }; -cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 1H }; -cmp.nz.f0.0(8) null<1>Q g6<4,4,1>Q g3<4,4,1>Q { align1 1Q }; +cmp.g.f0.0(8) nullUD g5.2<0,1,0>D 31D { align1 1Q }; +cmp.g.f0.0(8) nullUD g4.2<0,1,0>UD 0x0000001fUD { align1 1Q }; +(+f0.1) cmp.nz.f0.1(8) nullUD g0<8,8,1>UW g0<8,8,1>UW { align1 1Q }; +(+f0.1) cmp.nz.f0.1(16) nullUD g0<8,8,1>UW g0<8,8,1>UW { align1 1H }; +cmp.z.f0.0(16) nullUD g1<8,8,1>D 1024D { align1 2H }; +cmp.l.f0.0(16) nullUD g118<8,8,1>D 32D { align1 2H }; +cmp.nz.f0.0(8) nullUD g3<8,8,1>UD 0x00000000UD { align1 1Q }; +cmp.nz.f0.0(16) nullUD g3<8,8,1>UD 0x00000000UD { align1 1H }; +cmp.g.f0.0(16) nullUD g2.1<0,1,0>D 0D { align1 1H }; +cmp.nz.f0.0(8) null<2>UD g6<4,4,1>Q g3<4,4,1>Q { align1 1Q }; cmp.z.f0.0(8) g8<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; cmp.nz.f0.0(8) g2<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; -cmp.nz.f0.0(8) null<1>Q g9<4,4,1>Q g4<4,4,1>Q { align1 2Q }; +cmp.nz.f0.0(8) null<2>UD g9<4,4,1>Q g4<4,4,1>Q { align1 2Q }; cmp.z.f0.0(8) g17<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; cmp.nz.f0.0(8) g20<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; -cmp.z.f0.0(8) null<1>UD g5<8,8,1>UD 0x00000000UD { align1 1Q }; -cmp.z.f0.0(16) null<1>UD g15<8,8,1>UD 0x00000000UD { align1 1H }; +cmp.z.f0.0(8) nullUD g5<8,8,1>UD 0x00000000UD { align1 1Q }; +cmp.z.f0.0(16) nullUD g15<8,8,1>UD 0x00000000UD { align1 1H }; cmp.g.f0.0(16) g1<1>D g8<8,8,1>D 0D { align1 1H }; -cmp.ge.f0.0(8) null<1>UD g10<8,8,1>UD g8<8,8,1>UD { align1 1Q }; -cmp.ge.f0.0(8) null<1>DF g37<4,4,1>DF g26<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(8) null<1>Q g20<4,4,1>Q g25<4,4,1>Q { align1 1Q }; -cmp.l.f0.0(8) null<1>Q g2<4,4,1>Q g12<4,4,1>Q { align1 2Q }; -cmp.ge.f0.0(8) null<1>Q g20<4,4,1>Q g27<4,4,1>Q { align1 1Q }; -cmp.ge.f0.0(8) null<1>Q g2<4,4,1>Q g8<4,4,1>Q { align1 2Q }; -cmp.le.f0.0(8) null<1>UD g18<8,8,1>UD 0x000000ffUD { align1 1Q }; -cmp.le.f0.0(16) null<1>UD g32<8,8,1>UD 0x000000ffUD { align1 1H }; -cmp.z.f0.0(8) null<1>Q g12<4,4,1>Q g7<4,4,1>Q { align1 1Q }; -cmp.z.f0.0(8) null<1>Q g26<4,4,1>Q g12<4,4,1>Q { align1 2Q }; -cmp.g.f0.0(16) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1H }; +cmp.ge.f0.0(8) nullUD g10<8,8,1>UD g8<8,8,1>UD { align1 1Q }; +cmp.ge.f0.0(8) null<2>UD g37<4,4,1>DF g26<4,4,1>DF { align1 2Q }; +cmp.l.f0.0(8) null<2>UD g20<4,4,1>Q g25<4,4,1>Q { align1 1Q }; +cmp.l.f0.0(8) null<2>UD g2<4,4,1>Q g12<4,4,1>Q { align1 2Q }; +cmp.ge.f0.0(8) null<2>UD g20<4,4,1>Q g27<4,4,1>Q { align1 1Q }; +cmp.ge.f0.0(8) null<2>UD g2<4,4,1>Q g8<4,4,1>Q { align1 2Q }; +cmp.le.f0.0(8) nullUD g18<8,8,1>UD 0x000000ffUD { align1 1Q }; +cmp.le.f0.0(16) nullUD g32<8,8,1>UD 0x000000ffUD { align1 1H }; +cmp.z.f0.0(8) null<2>UD g12<4,4,1>Q g7<4,4,1>Q { align1 1Q }; +cmp.z.f0.0(8) null<2>UD g26<4,4,1>Q g12<4,4,1>Q { align1 2Q }; +cmp.g.f0.0(16) nullUD g4.2<0,1,0>UD 0x0000001fUD { align1 1H }; diff --git a/src/intel/compiler/brw/tests/gen9/cmp.expected b/src/intel/compiler/brw/tests/gen9/cmp.expected index 9e13e8c926b..2742e7a61ca 100644 --- a/src/intel/compiler/brw/tests/gen9/cmp.expected +++ b/src/intel/compiler/brw/tests/gen9/cmp.expected @@ -1,7 +1,7 @@ -10 00 60 01 e0 3a 00 20 80 02 8d 3e 00 00 80 bf +10 00 60 01 00 3a 00 20 80 02 8d 3e 00 00 80 bf 10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00 10 00 60 02 e8 3a 20 26 e0 05 8d 3a c4 01 00 00 -10 00 60 02 20 0a 00 20 e0 00 8d 0e 00 00 00 00 +10 00 60 02 00 0a 00 20 e0 00 8d 0e 00 00 00 00 10 00 60 01 28 0a a0 20 80 00 8d 0a 54 00 00 00 10 00 80 01 28 0a e0 20 a0 00 8d 0a 54 00 00 00 10 00 80 05 e8 3a 80 23 40 03 8d 3a 00 03 8d 00 @@ -9,96 +9,96 @@ 10 00 60 02 28 0a 60 25 40 05 8d 0a 44 00 00 00 10 00 60 01 c8 32 c0 2a d0 20 00 32 80 08 69 00 10 00 60 06 28 0a 80 2d 40 0d 8d 0e 00 00 00 00 -10 00 60 02 c0 32 00 20 d0 00 00 32 40 08 69 00 +10 00 60 02 00 32 00 40 d0 00 00 32 40 08 69 00 10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00 10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00 10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00 10 00 80 06 28 0a 60 24 a0 02 8d 0e 00 00 00 00 -10 10 60 02 c0 32 00 20 40 0d 69 32 40 06 69 00 +10 10 60 02 00 32 00 40 40 0d 69 32 40 06 69 00 10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00 10 00 60 05 00 02 00 20 80 01 8d 06 04 00 00 00 10 00 60 05 e8 3a a0 26 80 06 8d 3a 60 06 8d 00 10 00 60 04 e8 3a e0 26 80 06 8d 3a 60 06 8d 00 10 00 60 04 28 0a e0 21 80 21 8d 0e 01 00 00 00 -10 00 60 05 20 0a 00 20 c0 00 00 0e 02 00 00 00 -10 00 61 01 21 0a 00 20 00 01 8d 0e 00 00 00 00 +10 00 60 05 00 0a 00 20 c0 00 00 0e 02 00 00 00 +10 00 61 01 01 0a 00 20 00 01 8d 0e 00 00 00 00 10 00 80 02 28 0a 60 21 20 01 8d 0e 03 00 00 00 -10 00 81 01 21 0a 00 20 60 01 8d 0e 00 00 00 00 -10 00 60 01 20 0a 00 20 c0 02 8d 0e 01 00 00 00 -10 00 80 01 20 0a 00 20 e0 05 8d 0e 01 00 00 00 +10 00 81 01 01 0a 00 20 60 01 8d 0e 00 00 00 00 +10 00 60 01 00 0a 00 20 c0 02 8d 0e 01 00 00 00 +10 00 80 01 00 0a 00 20 e0 05 8d 0e 01 00 00 00 10 00 60 04 08 02 c0 23 a0 03 8d 02 bc 00 00 00 10 00 60 05 08 02 e0 23 a0 03 8d 02 ac 00 00 00 10 00 80 04 08 02 40 26 00 06 8d 02 fc 00 00 00 10 00 80 05 08 02 80 26 00 06 8d 02 ec 00 00 00 10 00 80 02 e8 3a 20 21 54 00 00 3a 24 00 00 00 -10 00 60 04 20 0a 00 20 c0 04 8d 0e 20 00 00 00 -10 00 60 04 c0 32 00 20 a0 02 69 32 a0 01 69 00 +10 00 60 04 00 0a 00 20 c0 04 8d 0e 20 00 00 00 +10 00 60 04 00 32 00 40 a0 02 69 32 a0 01 69 00 10 00 80 04 28 0a 60 20 24 00 00 0a 20 00 00 00 10 00 80 05 28 0a a0 20 24 00 00 0a 20 00 00 00 10 00 60 01 e8 3a 20 23 8c 00 00 3a 84 00 00 00 10 00 60 05 28 0a 20 24 a0 00 00 0e 01 00 00 00 10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00 10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00 -10 00 80 05 20 0a 00 20 c0 00 00 0e 01 00 00 00 +10 00 80 05 00 0a 00 20 c0 00 00 0e 01 00 00 00 10 00 80 01 e8 3a c0 27 80 01 8d 3a cc 00 00 00 -10 00 60 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 -10 00 80 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 +10 00 60 02 00 3a 00 20 40 00 00 3e 00 00 00 00 +10 00 80 02 00 3a 00 20 40 00 00 3e 00 00 00 00 10 00 80 04 00 02 00 20 c0 05 8d 06 40 00 00 00 -10 00 80 01 e0 3a 00 20 c0 01 8d 3a c4 00 00 00 -10 00 80 02 20 0a 00 20 c0 00 00 0e 00 00 00 00 +10 00 80 01 00 3a 00 20 c0 01 8d 3a c4 00 00 00 +10 00 80 02 00 0a 00 20 c0 00 00 0e 00 00 00 00 10 00 80 05 00 02 00 20 e0 04 8d 06 04 00 00 00 -10 00 60 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f -10 00 80 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f +10 00 60 06 00 3a 00 20 40 00 8d 3e 00 00 00 3f +10 00 80 06 00 3a 00 20 40 00 8d 3e 00 00 00 3f 10 00 60 06 e8 3a 80 22 ac 00 00 3e 00 00 00 00 -10 00 60 04 e0 3a 00 20 40 23 8d 3e 6b 0b 5e 5d +10 00 60 04 00 3a 00 20 40 23 8d 3e 6b 0b 5e 5d 10 00 60 03 e8 3a 00 2a 80 25 8d 3e 00 00 80 3f -10 00 80 04 20 0a 00 20 60 08 8d 0e 20 00 00 00 -10 00 60 03 e0 3a 00 20 80 0f 8d 3e 00 00 00 00 +10 00 80 04 00 0a 00 20 60 08 8d 0e 20 00 00 00 +10 00 60 03 00 3a 00 20 80 0f 8d 3e 00 00 00 00 10 10 60 01 e8 3a 80 20 a0 01 8a 3a 54 00 00 00 -10 00 80 03 e0 3a 00 20 00 0f 8d 3e 00 00 00 00 +10 00 80 03 00 3a 00 20 00 0f 8d 3e 00 00 00 00 10 00 80 03 e8 3a 40 20 20 22 8d 3e 00 00 80 3f -10 00 60 05 c0 32 00 20 a0 20 00 32 80 02 69 00 +10 00 60 05 00 32 00 40 a0 20 00 32 80 02 69 00 10 10 60 02 28 0a a0 23 c4 02 8a 0a 68 00 00 00 -10 10 60 05 c0 32 00 20 60 01 69 32 00 01 69 00 +10 10 60 05 00 32 00 40 60 01 69 32 00 01 69 00 10 10 60 02 e8 3a 20 29 c4 00 00 3a c0 01 8a 00 10 00 60 03 28 0a e0 20 40 00 00 0e 00 00 00 00 -10 00 60 05 e0 3a 00 20 90 00 00 3e 00 00 00 00 -10 00 80 05 e0 3a 00 20 d0 00 00 3e 00 00 00 00 -10 00 60 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 -10 00 80 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 -10 00 80 04 e0 3a 00 20 60 04 8d 3e 00 00 00 3f +10 00 60 05 00 3a 00 20 90 00 00 3e 00 00 00 00 +10 00 80 05 00 3a 00 20 d0 00 00 3e 00 00 00 00 +10 00 60 06 00 0a 00 20 40 00 8d 0e 32 00 00 00 +10 00 80 06 00 0a 00 20 40 00 8d 0e 32 00 00 00 +10 00 80 04 00 3a 00 20 60 04 8d 3e 00 00 00 3f 10 00 60 06 08 02 80 20 40 00 00 06 01 00 00 00 10 00 60 03 08 02 a0 20 40 00 00 06 01 00 00 00 10 00 80 06 08 02 a0 20 40 00 00 06 01 00 00 00 10 00 80 03 08 02 e0 20 40 00 00 06 01 00 00 00 10 00 80 06 e8 3a 20 2f 60 03 8d 3e 9a 3f 1c 46 10 10 60 01 28 0a a0 20 c0 01 8a 0a 64 00 00 00 -10 00 60 03 20 0a 00 20 a8 00 00 0e 1f 00 00 00 +10 00 60 03 00 0a 00 20 a8 00 00 0e 1f 00 00 00 10 00 60 03 00 02 00 20 88 00 00 06 1f 00 00 00 -10 00 61 02 41 12 00 20 00 00 8d 12 00 00 8d 00 -10 00 81 02 41 12 00 20 00 00 8d 12 00 00 8d 00 -10 20 80 01 20 0a 00 20 20 00 8d 0e 00 04 00 00 -10 20 80 05 20 0a 00 20 c0 0e 8d 0e 20 00 00 00 +10 00 61 02 01 12 00 20 00 00 8d 12 00 00 8d 00 +10 00 81 02 01 12 00 20 00 00 8d 12 00 00 8d 00 +10 20 80 01 00 0a 00 20 20 00 8d 0e 00 04 00 00 +10 20 80 05 00 0a 00 20 c0 0e 8d 0e 20 00 00 00 10 00 60 02 00 02 00 20 60 00 8d 06 00 00 00 00 10 00 80 02 00 02 00 20 60 00 8d 06 00 00 00 00 -10 00 80 03 20 0a 00 20 44 00 00 0e 00 00 00 00 -10 00 60 02 20 4b 00 20 c0 00 69 4a 60 00 69 00 +10 00 80 03 00 0a 00 20 44 00 00 0e 00 00 00 00 +10 00 60 02 00 4a 00 40 c0 00 69 4a 60 00 69 00 10 00 60 01 28 4b 00 21 a0 00 69 4a 60 00 69 00 10 00 60 02 28 4b 40 20 a0 00 69 4a 60 00 69 00 -10 10 60 02 20 4b 00 20 20 01 69 4a 80 00 69 00 +10 10 60 02 00 4a 00 40 20 01 69 4a 80 00 69 00 10 10 60 01 28 4b 20 22 60 01 69 4a 80 00 69 00 10 10 60 02 28 4b 80 22 60 01 69 4a 80 00 69 00 10 00 60 01 00 02 00 20 a0 00 8d 06 00 00 00 00 10 00 80 01 00 02 00 20 e0 01 8d 06 00 00 00 00 10 00 80 03 28 0a 20 20 00 01 8d 0e 00 00 00 00 10 00 60 04 00 02 00 20 40 01 8d 02 00 01 8d 00 -10 10 60 04 c0 32 00 20 a0 04 69 32 40 03 69 00 -10 00 60 05 20 4b 00 20 80 02 69 4a 20 03 69 00 -10 10 60 05 20 4b 00 20 40 00 69 4a 80 01 69 00 -10 00 60 04 20 4b 00 20 80 02 69 4a 60 03 69 00 -10 10 60 04 20 4b 00 20 40 00 69 4a 00 01 69 00 +10 10 60 04 00 32 00 40 a0 04 69 32 40 03 69 00 +10 00 60 05 00 4a 00 40 80 02 69 4a 20 03 69 00 +10 10 60 05 00 4a 00 40 40 00 69 4a 80 01 69 00 +10 00 60 04 00 4a 00 40 80 02 69 4a 60 03 69 00 +10 10 60 04 00 4a 00 40 40 00 69 4a 00 01 69 00 10 00 60 06 00 02 00 20 40 02 8d 06 ff 00 00 00 10 00 80 06 00 02 00 20 00 04 8d 06 ff 00 00 00 -10 00 60 01 20 4b 00 20 80 01 69 4a e0 00 69 00 -10 10 60 01 20 4b 00 20 40 03 69 4a 80 01 69 00 +10 00 60 01 00 4a 00 40 80 01 69 4a e0 00 69 00 +10 10 60 01 00 4a 00 40 40 03 69 4a 80 01 69 00 10 00 80 03 00 02 00 20 88 00 00 06 1f 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/math.asm b/src/intel/compiler/brw/tests/gen9/math.asm index d6a54d2c389..142e2ddc115 100644 --- a/src/intel/compiler/brw/tests/gen9/math.asm +++ b/src/intel/compiler/brw/tests/gen9/math.asm @@ -1,31 +1,31 @@ -math sqrt(16) g20<1>F g18<8,8,1>F null<8,8,1>F { align1 1H }; -math inv(8) g95<1>F g94<8,8,1>F null<8,8,1>F { align1 1Q }; -math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 1H }; +math sqrt(16) g20<1>F g18<8,8,1>F nullUD { align1 1H }; +math inv(8) g95<1>F g94<8,8,1>F nullUD { align1 1Q }; +math inv(16) g10<1>F g8<8,8,1>F nullUD { align1 1H }; math intmod(8) g3<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 1Q }; math intmod(8) g4<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 2Q }; -math sqrt(8) g24<1>F g23<8,8,1>F null<8,8,1>F { align1 1Q }; -math rsq(8) g5<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; +math sqrt(8) g24<1>F g23<8,8,1>F nullUD { align1 1Q }; +math rsq(8) g5<1>F g2<8,8,1>F nullUD { align1 1Q }; math pow(8) g11<1>F g10<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1Q }; math pow(16) g18<1>F g16<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1H }; -math log(8) g7<1>F g6<8,8,1>F null<8,8,1>F { align1 1Q }; -math log(16) g11<1>F g9<8,8,1>F null<8,8,1>F { align1 1H }; -math cos(8) g3<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; -math cos(16) g4<1>F g2<8,8,1>F null<8,8,1>F { align1 1H }; +math log(8) g7<1>F g6<8,8,1>F nullUD { align1 1Q }; +math log(16) g11<1>F g9<8,8,1>F nullUD { align1 1H }; +math cos(8) g3<1>F g2<8,8,1>F nullUD { align1 1Q }; +math cos(16) g4<1>F g2<8,8,1>F nullUD { align1 1H }; math intdiv(8) g4<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 1Q }; math intdiv(8) g5<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 2Q }; math intdiv(8) g24<1>D g4<0,1,0>D g2.2<0,1,0>D { align1 1Q }; -math sin(8) g10<1>F g9<8,8,1>F null<8,8,1>F { align1 1Q }; -math rsq(16) g68<1>F g66<8,8,1>F null<8,8,1>F { align1 1H }; -math exp(8) g124<1>F g10<8,8,1>F null<8,8,1>F { align1 1Q }; -math exp(16) g120<1>F g7<8,8,1>F null<8,8,1>F { align1 1H }; +math sin(8) g10<1>F g9<8,8,1>F nullUD { align1 1Q }; +math rsq(16) g68<1>F g66<8,8,1>F nullUD { align1 1H }; +math exp(8) g124<1>F g10<8,8,1>F nullUD { align1 1Q }; +math exp(16) g120<1>F g7<8,8,1>F nullUD { align1 1H }; math intdiv(8) g5<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 2Q }; -math sin(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; +math sin(16) g3<1>F g2<0,1,0>F nullUD { align1 1H }; math.sat pow(8) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1Q }; math.sat pow(16) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; -math.sat sqrt(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat sqrt(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; -math.sat exp(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat exp(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; -math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F null<8,8,1>F { align1 1Q }; -math.sat inv(8) g124<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat log(8) g127<1>F g7<8,8,1>F null<8,8,1>F { align1 1Q }; +math.sat sqrt(8) g3<1>F g2<0,1,0>F nullUD { align1 1Q }; +math.sat sqrt(16) g3<1>F g2<0,1,0>F nullUD { align1 1H }; +math.sat exp(8) g3<1>F g2<0,1,0>F nullUD { align1 1Q }; +math.sat exp(16) g3<1>F g2<0,1,0>F nullUD { align1 1H }; +math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F nullUD { align1 1Q }; +math.sat inv(8) g124<1>F g2<0,1,0>F nullUD { align1 1Q }; +math.sat log(8) g127<1>F g7<8,8,1>F nullUD { align1 1Q }; diff --git a/src/intel/compiler/brw/tests/gen9/math.expected b/src/intel/compiler/brw/tests/gen9/math.expected index 9837a7cee3f..ac7f7a511af 100644 --- a/src/intel/compiler/brw/tests/gen9/math.expected +++ b/src/intel/compiler/brw/tests/gen9/math.expected @@ -1,31 +1,31 @@ -38 00 80 04 e8 3a 80 22 40 02 8d 38 00 00 8d 00 -38 00 60 01 e8 3a e0 2b c0 0b 8d 38 00 00 8d 00 -38 00 80 01 e8 3a 40 21 00 01 8d 38 00 00 8d 00 +38 00 80 04 e8 3a 80 22 40 02 8d 00 00 00 00 00 +38 00 60 01 e8 3a e0 2b c0 0b 8d 00 00 00 00 00 +38 00 80 01 e8 3a 40 21 00 01 8d 00 00 00 00 00 38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00 38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00 -38 00 60 04 e8 3a 00 23 e0 02 8d 38 00 00 8d 00 -38 00 60 05 e8 3a a0 20 40 00 8d 38 00 00 8d 00 +38 00 60 04 e8 3a 00 23 e0 02 8d 00 00 00 00 00 +38 00 60 05 e8 3a a0 20 40 00 8d 00 00 00 00 00 38 00 60 0a e8 3a 60 21 40 01 8d 3e 66 66 fc 42 38 00 80 0a e8 3a 40 22 00 02 8d 3e 66 66 fc 42 -38 00 60 02 e8 3a e0 20 c0 00 8d 38 00 00 8d 00 -38 00 80 02 e8 3a 60 21 20 01 8d 38 00 00 8d 00 -38 00 60 07 e8 3a 60 20 40 00 8d 38 00 00 8d 00 -38 00 80 07 e8 3a 80 20 40 00 8d 38 00 00 8d 00 +38 00 60 02 e8 3a e0 20 c0 00 8d 00 00 00 00 00 +38 00 80 02 e8 3a 60 21 20 01 8d 00 00 00 00 00 +38 00 60 07 e8 3a 60 20 40 00 8d 00 00 00 00 00 +38 00 80 07 e8 3a 80 20 40 00 8d 00 00 00 00 00 38 00 60 0c 08 02 80 20 20 00 00 02 30 00 00 00 38 10 60 0c 08 02 a0 20 20 00 00 02 30 00 00 00 38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00 -38 00 60 06 e8 3a 40 21 20 01 8d 38 00 00 8d 00 -38 00 80 05 e8 3a 80 28 40 08 8d 38 00 00 8d 00 -38 00 60 03 e8 3a 80 2f 40 01 8d 38 00 00 8d 00 -38 00 80 03 e8 3a 00 2f e0 00 8d 38 00 00 8d 00 +38 00 60 06 e8 3a 40 21 20 01 8d 00 00 00 00 00 +38 00 80 05 e8 3a 80 28 40 08 8d 00 00 00 00 00 +38 00 60 03 e8 3a 80 2f 40 01 8d 00 00 00 00 00 +38 00 80 03 e8 3a 00 2f e0 00 8d 00 00 00 00 00 38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00 -38 00 80 06 e8 3a 60 20 40 00 00 38 00 00 8d 00 +38 00 80 06 e8 3a 60 20 40 00 00 00 00 00 00 00 38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 -38 00 60 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 80 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 60 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 80 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 60 85 e8 3a e0 2f e0 20 8d 38 00 00 8d 00 -38 00 60 81 e8 3a 80 2f 40 00 00 38 00 00 8d 00 -38 00 60 82 e8 3a e0 2f e0 00 8d 38 00 00 8d 00 +38 00 60 84 e8 3a 60 20 40 00 00 00 00 00 00 00 +38 00 80 84 e8 3a 60 20 40 00 00 00 00 00 00 00 +38 00 60 83 e8 3a 60 20 40 00 00 00 00 00 00 00 +38 00 80 83 e8 3a 60 20 40 00 00 00 00 00 00 00 +38 00 60 85 e8 3a e0 2f e0 20 8d 00 00 00 00 00 +38 00 60 81 e8 3a 80 2f 40 00 00 00 00 00 00 00 +38 00 60 82 e8 3a e0 2f e0 00 8d 00 00 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/mov.asm b/src/intel/compiler/brw/tests/gen9/mov.asm index 833631bb9e2..5b55c077181 100644 --- a/src/intel/compiler/brw/tests/gen9/mov.asm +++ b/src/intel/compiler/brw/tests/gen9/mov.asm @@ -6,7 +6,7 @@ mov.sat(8) g124<1>F g8<8,8,1>F { align1 1Q }; mov(8) g61<2>D g22<8,8,1>D { align1 1Q }; mov(8) g21<1>D g59<8,4,2>UD { align1 1Q }; mov(8) g4<1>D -1D { align1 1Q }; -mov.nz.f0.0(8) null<1>D g4<8,8,1>D { align1 1Q }; +mov.nz.f0.0(8) nullUD g4<8,8,1>D { align1 1Q }; mov(1) g2.2<1>UD 0x00000000UD { align1 WE_all 1N }; mov(4) g114<1>F g2.3<8,2,4>F { align1 WE_all 1N }; mov(8) g126<1>F g4<8,8,1>D { align1 1Q }; @@ -14,7 +14,7 @@ mov(16) g124<1>F g4<8,8,1>D { align1 1H }; mov(16) g120<1>F g124<8,8,1>F { align1 1H }; mov(16) g124<1>F 0x0F /* 0F */ { align1 1H }; mov(16) g124<1>D 1065353216D { align1 1H }; -mov.nz.f0.0(16) null<1>D g2<0,1,0>D { align1 1H }; +mov.nz.f0.0(16) nullUD g2<0,1,0>D { align1 1H }; mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; mov(16) g20<1>UD g0.1<0,1,0>UD { align1 1H }; mov(16) g6<1>D g3<8,8,1>UW { align1 1H }; @@ -117,14 +117,14 @@ mov(8) g12<1>UW g8<16,8,2>UW { align1 WE_all mov.sat(16) g13<1>F 0x3f800000F /* 1F */ { align1 1H }; mov(16) g19<2>UW g17<8,8,1>F { align1 1H }; mov(16) g4<1>UW g13<16,8,2>UW { align1 WE_all 1H }; -mov.nz.f0.0(8) null<1>D 0x00000000UD { align1 1Q }; -mov.nz.f0.0(16) null<1>D 0x00000000UD { align1 1H }; +mov.nz.f0.0(8) nullUD 0x00000000UD { align1 1Q }; +mov.nz.f0.0(16) nullUD 0x00000000UD { align1 1H }; mov(4) g3<1>UD tm0<4,4,1>UD { align1 WE_all 1N }; (+f0.0.all16h) mov(1) g1<1>D -1D { align1 WE_all 1N }; mov(8) g9<1>F g2<0,1,0>UB { align1 1Q }; mov(16) g6<1>F g2<0,1,0>UB { align1 1H }; mov(16) g10<2>HF g4<8,8,1>F { align1 1H }; -mov.z.f0.0(8) null<1>UD g2<8,8,1>UD { align1 1Q }; +mov.z.f0.0(8) nullUD g2<8,8,1>UD { align1 1Q }; mov.sat(8) g125<1>F g9<8,8,1>UD { align1 1Q }; mov.z.f0.0(16) g1<1>UD g0.7<0,1,0>UD { align1 1H }; mov.z.f0.0(8) g18<1>D g17<8,8,1>F { align1 1Q }; @@ -134,6 +134,6 @@ mov(8) g2<1>D 0x00000000UD { align1 1Q }; mov(16) g2<1>D 0x00000000UD { align1 1H }; (+f0.0.all8h) mov(1) g7<1>D -1D { align1 WE_all 1N }; mov(8) g127<1>UB g2<0,1,0>UB { align1 WE_all 1Q }; -mov.z.f0.0(8) null<1>D g24<8,8,1>F { align1 1Q }; -mov.z.f0.0(16) null<1>D g76<8,8,1>F { align1 1H }; +mov.z.f0.0(8) nullUD g24<8,8,1>F { align1 1Q }; +mov.z.f0.0(16) nullUD g76<8,8,1>F { align1 1H }; mov(16) g7<1>D g2<16,8,2>B { align1 1H }; diff --git a/src/intel/compiler/brw/tests/gen9/mov.expected b/src/intel/compiler/brw/tests/gen9/mov.expected index c1dc96d9d60..f6414f0ab56 100644 --- a/src/intel/compiler/brw/tests/gen9/mov.expected +++ b/src/intel/compiler/brw/tests/gen9/mov.expected @@ -6,7 +6,7 @@ 01 00 60 00 28 0a a0 47 c0 02 8d 00 00 00 00 00 01 00 60 00 28 02 a0 22 60 07 8a 00 00 00 00 00 01 00 60 00 28 0e 80 20 00 00 00 08 ff ff ff ff -01 00 60 02 20 0a 00 20 80 00 8d 00 00 00 00 00 +01 00 60 02 00 0a 00 20 80 00 8d 00 00 00 00 00 01 00 00 00 0c 06 48 20 00 00 00 00 00 00 00 00 01 00 40 00 ec 3a 40 2e 4c 00 87 00 00 00 00 00 01 00 60 00 e8 0a c0 2f 80 00 8d 00 00 00 00 00 @@ -14,7 +14,7 @@ 01 00 80 00 e8 3a 00 2f 80 0f 8d 00 00 00 00 00 01 00 80 00 e8 3e 80 2f 00 00 00 38 00 00 00 00 01 00 80 00 28 0e 80 2f 00 00 00 08 00 00 80 3f -01 00 80 02 20 0a 00 20 40 00 00 00 00 00 00 00 +01 00 80 02 00 0a 00 20 40 00 00 00 00 00 00 00 01 00 60 00 4c 36 60 20 00 00 00 30 10 32 54 76 01 00 80 00 08 02 80 22 04 00 00 00 00 00 00 00 01 00 80 00 28 12 c0 20 60 00 8d 00 00 00 00 00 @@ -117,8 +117,8 @@ 01 00 80 80 e8 3e a0 21 00 00 00 38 00 00 80 3f 01 00 80 00 48 3a 60 42 20 02 8d 00 00 00 00 00 01 00 80 00 4c 12 80 20 a0 01 ae 00 00 00 00 00 -01 00 60 02 20 06 00 20 00 00 00 00 00 00 00 00 -01 00 80 02 20 06 00 20 00 00 00 00 00 00 00 00 +01 00 60 02 00 06 00 20 00 00 00 00 00 00 00 00 +01 00 80 02 00 06 00 20 00 00 00 00 00 00 00 00 01 00 40 00 0c 00 60 20 00 18 69 00 00 00 00 00 01 00 0b 00 2c 0e 20 20 00 00 00 08 ff ff ff ff 01 00 60 00 e8 22 20 21 40 00 00 00 00 00 00 00 @@ -134,6 +134,6 @@ 01 00 80 00 28 06 40 20 00 00 00 00 00 00 00 00 01 00 09 00 2c 0e e0 20 00 00 00 08 ff ff ff ff 01 00 60 00 8c 22 e0 2f 40 00 00 00 00 00 00 00 -01 00 60 01 20 3a 00 20 00 03 8d 00 00 00 00 00 -01 00 80 01 20 3a 00 20 80 09 8d 00 00 00 00 00 +01 00 60 01 00 3a 00 20 00 03 8d 00 00 00 00 00 +01 00 80 01 00 3a 00 20 80 09 8d 00 00 00 00 00 01 00 80 00 28 2a e0 20 40 00 ae 00 00 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/mul.asm b/src/intel/compiler/brw/tests/gen9/mul.asm index 36f4a1bcf57..c94e31b6974 100644 --- a/src/intel/compiler/brw/tests/gen9/mul.asm +++ b/src/intel/compiler/brw/tests/gen9/mul.asm @@ -13,7 +13,7 @@ mul(8) g39<1>DF g3.3<0,1,0>DF g3.3<0,1,0>DF { align1 2Q }; mul.z.f0.0(16) g6<1>F g2<0,1,0>F g4<8,8,1>F { align1 1H }; mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q }; mul.sat(16) g9<1>F g3<8,8,1>F g7<8,8,1>F { align1 1H }; -mul.l.f0.0(8) null<1>F g6<0,1,0>F g5.7<0,1,0>F { align1 1Q }; +mul.l.f0.0(8) nullUD g6<0,1,0>F g5.7<0,1,0>F { align1 1Q }; mul.sat(8) g8<1>DF g34<4,4,1>DF g5<4,4,1>DF { align1 1Q }; mul(8) g4<1>UQ g8<4,4,1>UD g12<4,4,1>UD { align1 1Q }; mul(8) g20<1>UQ g5<4,4,1>UD g13<4,4,1>UD { align1 2Q }; @@ -23,7 +23,7 @@ mul.l.f0.0(8) g20<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 mul.l.f0.0(16) g32<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1H }; mul(1) g6<1>UD g12<0,1,0>UD 0x00000101UD { align1 WE_all 1N }; mul(8) g21<1>Q g6<4,4,1>D g14<4,4,1>D { align1 2Q }; -mul.l.f0.0(16) null<1>F g2.2<0,1,0>F g2.1<0,1,0>F { align1 1H }; +mul.l.f0.0(16) nullUD g2.2<0,1,0>F g2.1<0,1,0>F { align1 1H }; mul(8) g6<1>UW g6<8,8,1>UW 0x0808UW { align1 1Q }; mul(16) g15<1>UW g14<16,16,1>UW 0x0808UW { align1 1H }; mul.nz.f0.0(8) g6<1>F g12<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1Q }; diff --git a/src/intel/compiler/brw/tests/gen9/mul.expected b/src/intel/compiler/brw/tests/gen9/mul.expected index 1a1a79c6467..f8661892af1 100644 --- a/src/intel/compiler/brw/tests/gen9/mul.expected +++ b/src/intel/compiler/brw/tests/gen9/mul.expected @@ -13,7 +13,7 @@ 41 00 80 01 e8 3a c0 20 40 00 00 3a 80 00 8d 00 41 00 60 80 e8 3a 20 22 80 00 8d 3a 00 02 8d 00 41 00 80 80 e8 3a 20 21 60 00 8d 3a e0 00 8d 00 -41 00 60 05 e0 3a 00 20 c0 00 00 3a bc 00 00 00 +41 00 60 05 00 3a 00 20 c0 00 00 3a bc 00 00 00 41 00 60 80 c8 32 00 21 40 04 69 32 a0 00 69 00 41 00 60 00 08 03 80 20 00 01 69 02 80 01 69 00 41 10 60 00 08 03 80 22 a0 00 69 02 a0 01 69 00 @@ -23,7 +23,7 @@ 41 00 80 05 e8 3a 00 24 40 00 8d 3e 00 00 70 42 41 00 00 00 0c 02 c0 20 80 01 00 06 01 01 00 00 41 10 60 00 28 0b a0 22 c0 00 69 0a c0 01 69 00 -41 00 80 05 e0 3a 00 20 48 00 00 3a 44 00 00 00 +41 00 80 05 00 3a 00 20 48 00 00 3a 44 00 00 00 41 00 60 00 48 12 c0 20 c0 00 8d 16 08 08 08 08 41 00 80 00 48 12 e0 21 c0 01 b1 16 08 08 08 08 41 00 60 02 e8 3a c0 20 80 01 8d 3e 00 80 80 3f diff --git a/src/intel/compiler/brw/tests/gen9/or.asm b/src/intel/compiler/brw/tests/gen9/or.asm index 3bfcc980749..17fd8ac2de9 100644 --- a/src/intel/compiler/brw/tests/gen9/or.asm +++ b/src/intel/compiler/brw/tests/gen9/or.asm @@ -1,8 +1,8 @@ or(8) g53<1>UD g49<8,8,1>UD g21<8,8,1>UD { align1 1Q }; -or.nz.f0.0(8) null<1>UD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q }; +or.nz.f0.0(8) nullUD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q }; or.nz.f0.0(8) g5<1>UD g62<8,8,1>UD g67<8,8,1>UD { align1 1Q }; or(8) g5<1>UD g106.1<8,4,2>UD 0x7ff00000UD { align1 2Q }; -or.nz.f0.0(16) null<1>UD g35<8,8,1>UD g32<8,8,1>UD { align1 1H }; +or.nz.f0.0(16) nullUD g35<8,8,1>UD g32<8,8,1>UD { align1 1H }; or(16) g36<1>UD g34<8,8,1>UD g20<8,8,1>UD { align1 1H }; or.nz.f0.0(16) g53<1>UD g51<8,8,1>UD g49<8,8,1>UD { align1 1H }; or(1) g8<1>UD g8<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N }; @@ -19,5 +19,5 @@ or(16) g37<1>UD ~g2.2<0,1,0>D g35<8,8,1>UD { align1 1H }; or(8) g9<1>D ~g8<8,8,1>D ~g7<8,8,1>D { align1 1Q }; or(16) g13<1>D ~g11<8,8,1>D ~g9<8,8,1>D { align1 1H }; or(1) g14<1>UD g14<0,1,0>UD g19<0,1,0>UD { align1 WE_all 3N }; -or.z.f0.0(8) null<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 1Q }; -or.z.f0.0(16) null<1>UD g17<8,8,1>UD g19<8,8,1>UD { align1 1H }; +or.z.f0.0(8) nullUD g5<8,8,1>UD g6<8,8,1>UD { align1 1Q }; +or.z.f0.0(16) nullUD g17<8,8,1>UD g19<8,8,1>UD { align1 1H }; diff --git a/src/intel/compiler/brw/tests/gen9/rndd.asm b/src/intel/compiler/brw/tests/gen9/rndd.asm index 463ef808ca9..8be41ba03cc 100644 --- a/src/intel/compiler/brw/tests/gen9/rndd.asm +++ b/src/intel/compiler/brw/tests/gen9/rndd.asm @@ -1,5 +1,5 @@ rndd(8) g22<1>F g17<0,1,0>F { align1 1Q }; rndd(16) g7<1>F g5<8,8,1>F { align1 1H }; -rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q }; -rndd.z.f0.0(16) null<1>F g39<8,8,1>F { align1 1H }; +rndd.z.f0.0(8) nullUD g17<8,8,1>F { align1 1Q }; +rndd.z.f0.0(16) nullUD g39<8,8,1>F { align1 1H }; rndd.sat(8) g124<1>F g10<8,8,1>F { align1 1Q }; diff --git a/src/intel/compiler/brw/tests/gen9/rndd.expected b/src/intel/compiler/brw/tests/gen9/rndd.expected index ff7ca82d09f..7475d831e39 100644 --- a/src/intel/compiler/brw/tests/gen9/rndd.expected +++ b/src/intel/compiler/brw/tests/gen9/rndd.expected @@ -1,5 +1,5 @@ 45 00 60 00 e8 3a c0 22 20 02 00 00 00 00 00 00 45 00 80 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00 -45 00 60 01 e0 3a 00 20 20 02 8d 00 00 00 00 00 -45 00 80 01 e0 3a 00 20 e0 04 8d 00 00 00 00 00 +45 00 60 01 00 3a 00 20 20 02 8d 00 00 00 00 00 +45 00 80 01 00 3a 00 20 e0 04 8d 00 00 00 00 00 45 00 60 80 e8 3a 80 2f 40 01 8d 00 00 00 00 00 diff --git a/src/intel/compiler/brw/tests/gen9/send.asm b/src/intel/compiler/brw/tests/gen9/send.asm index 99d55feb5d1..947c305f402 100644 --- a/src/intel/compiler/brw/tests/gen9/send.asm +++ b/src/intel/compiler/brw/tests/gen9/send.asm @@ -1,14 +1,14 @@ -send(8) null<1>F g123<8,8,1>F 0x8a080017 +send(8) nullUD g123<8,8,1>F 0x8a080017 urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g13<8,8,1>F 0x12080007 +send(8) nullUD g13<8,8,1>F 0x12080007 urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080027 +send(8) nullUD g123<8,8,1>F 0x8a080027 urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(16) g9<1>UD g2<0,1,0>UD 0x02280300 hdc:ro MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080017 +send(8) nullUD g119<8,8,1>F 0x92080017 urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(16) null<1>UW g127<8,8,1>UW 0x82000010 +send(16) nullUD g127<8,8,1>UW 0x82000010 ts/btd MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; send(8) g124<1>UW g13<8,8,1>UD 0x0643a001 sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; @@ -16,31 +16,31 @@ send(16) g120<1>UW g23<8,8,1>UD 0x0c85a001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; send(8) g10<1>UD g2<8,8,1>UD 0x02480028 urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g8<8,8,1>F 0x140a0017 +send(8) nullUD g8<8,8,1>F 0x140a0017 urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0017 +send(8) nullUD g118<8,8,1>F 0x940a0017 urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; send(8) g2<1>UW g10<8,8,1>UD 0x08427001 sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; send(16) g2<1>UW g18<8,8,1>UD 0x10847001 sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(8) null<1>F g11<8,8,1>UD 0x0c0a0037 +send(8) nullUD g11<8,8,1>UD 0x0c0a0037 urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a080027 +send(8) nullUD g6<8,8,1>UD 0x0a080027 urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088017 +send(8) nullUD g6<8,8,1>UD 0x0c088017 urb MsgDesc: 1 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a088017 +send(8) nullUD g6<8,8,1>UD 0x0a088017 urb MsgDesc: 1 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x08088017 +send(8) nullUD g6<8,8,1>UD 0x08088017 urb MsgDesc: 1 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>UD 0x06088017 +send(8) nullUD g2<8,8,1>UD 0x06088017 urb MsgDesc: 1 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088007 +send(8) nullUD g6<8,8,1>UD 0x0c088007 urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a088007 +send(8) nullUD g6<8,8,1>UD 0x0a088007 urb MsgDesc: 0 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g125<8,8,1>UD 0x86088007 +send(8) nullUD g125<8,8,1>UD 0x86088007 urb MsgDesc: 0 SIMD8 write masked mlen 3 rlen 0 { align1 1Q EOT }; send(8) g7<1>UW g7<8,8,1>UD 0x0443a000 sampler MsgDesc: ld_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; @@ -52,11 +52,11 @@ send(16) g25<1>UW g16<8,8,1>UD 0x0444a001 sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; send(16) g14<1>UW g7<8,8,1>UD 0x0e8c8001 sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; -send(8) null<1>F g11<8,8,1>F 0x12080017 +send(8) nullUD g11<8,8,1>F 0x12080017 urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>F 0x12080037 +send(8) nullUD g20<8,8,1>F 0x12080037 urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080057 +send(8) nullUD g123<8,8,1>F 0x8a080057 urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g9<1>UW g6<8,8,1>UD 0x0613d001 sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; @@ -88,7 +88,7 @@ send(8) g124<1>UW g13<8,8,1>UD 0x064a8000 sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; send(8) g12<1>UW g5<8,8,1>UD 0x02427000 sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080037 +send(8) nullUD g123<8,8,1>F 0x8a080037 urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g6<1>UW g11<8,8,1>UD 0x144a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q }; @@ -114,17 +114,17 @@ send(16) g12<1>UW g21<8,8,1>UD 0x122c6102 sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H }; send(8) g124<1>UW g3<8,8,1>UD 0x0a43e000 sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080027 +send(8) nullUD g119<8,8,1>F 0x92080027 urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g2<1>UW g3<8,8,1>UD 0x0643d000 sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0a080037 +send(8) nullUD g7<8,8,1>UD 0x0a080037 urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a080047 +send(8) nullUD g8<8,8,1>UD 0x0a080047 urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>F 0x0c0a0017 +send(8) nullUD g29<8,8,1>F 0x0c0a0017 urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0017 +send(8) nullUD g122<8,8,1>F 0x8c0a0017 urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g13<1>UW g10<8,8,1>UD 0x02320001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; @@ -136,13 +136,13 @@ send(8) g2<1>UW g13<8,8,1>UD 0x0c4b1001 sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; send(16) g18<1>UW g7<8,8,1>UD 0x168d1001 sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; -send(8) null<1>F g6<8,8,1>UD 0x0a088027 +send(8) nullUD g6<8,8,1>UD 0x0a088027 urb MsgDesc: 2 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0a088037 +send(8) nullUD g7<8,8,1>UD 0x0a088037 urb MsgDesc: 3 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a088047 +send(8) nullUD g8<8,8,1>UD 0x0a088047 urb MsgDesc: 4 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x0a088057 +send(8) nullUD g9<8,8,1>UD 0x0a088057 urb MsgDesc: 5 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; send(8) g124<1>UW g3<8,8,1>UD 0x06427000 sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; @@ -196,133 +196,133 @@ send(8) g18<1>UD g30<8,8,1>UD 0x02480608 urb MsgDesc: 96 SIMD8 read mlen 1 rlen 4 { align1 1Q }; send(8) g22<1>UD g30<8,8,1>UD 0x02480808 urb MsgDesc: 128 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a0a8217 +send(8) nullUD g6<8,8,1>UD 0x0a0a8217 urb MsgDesc: 33 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0a0a8227 +send(8) nullUD g11<8,8,1>UD 0x0a0a8227 urb MsgDesc: 34 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0a0a8237 +send(8) nullUD g12<8,8,1>UD 0x0a0a8237 urb MsgDesc: 35 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0a0a8247 +send(8) nullUD g13<8,8,1>UD 0x0a0a8247 urb MsgDesc: 36 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0a0a8257 +send(8) nullUD g14<8,8,1>UD 0x0a0a8257 urb MsgDesc: 37 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0a0a8267 +send(8) nullUD g15<8,8,1>UD 0x0a0a8267 urb MsgDesc: 38 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a0a8277 +send(8) nullUD g16<8,8,1>UD 0x0a0a8277 urb MsgDesc: 39 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a0a8287 +send(8) nullUD g17<8,8,1>UD 0x0a0a8287 urb MsgDesc: 40 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a0a8297 +send(8) nullUD g18<8,8,1>UD 0x0a0a8297 urb MsgDesc: 41 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a0a82a7 +send(8) nullUD g19<8,8,1>UD 0x0a0a82a7 urb MsgDesc: 42 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0a82b7 +send(8) nullUD g20<8,8,1>UD 0x0a0a82b7 urb MsgDesc: 43 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0a82c7 +send(8) nullUD g21<8,8,1>UD 0x0a0a82c7 urb MsgDesc: 44 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0a82d7 +send(8) nullUD g22<8,8,1>UD 0x0a0a82d7 urb MsgDesc: 45 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0a82e7 +send(8) nullUD g23<8,8,1>UD 0x0a0a82e7 urb MsgDesc: 46 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0a82f7 +send(8) nullUD g24<8,8,1>UD 0x0a0a82f7 urb MsgDesc: 47 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0a8307 +send(8) nullUD g25<8,8,1>UD 0x0a0a8307 urb MsgDesc: 48 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a0a8317 +send(8) nullUD g26<8,8,1>UD 0x0a0a8317 urb MsgDesc: 49 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a0a8327 +send(8) nullUD g27<8,8,1>UD 0x0a0a8327 urb MsgDesc: 50 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a0a8337 +send(8) nullUD g28<8,8,1>UD 0x0a0a8337 urb MsgDesc: 51 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a0a8347 +send(8) nullUD g29<8,8,1>UD 0x0a0a8347 urb MsgDesc: 52 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a0a8357 +send(8) nullUD g30<8,8,1>UD 0x0a0a8357 urb MsgDesc: 53 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a0a8367 +send(8) nullUD g31<8,8,1>UD 0x0a0a8367 urb MsgDesc: 54 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a0a8377 +send(8) nullUD g32<8,8,1>UD 0x0a0a8377 urb MsgDesc: 55 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a0a8387 +send(8) nullUD g33<8,8,1>UD 0x0a0a8387 urb MsgDesc: 56 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a0a8397 +send(8) nullUD g34<8,8,1>UD 0x0a0a8397 urb MsgDesc: 57 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a0a83a7 +send(8) nullUD g35<8,8,1>UD 0x0a0a83a7 urb MsgDesc: 58 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0a83b7 +send(8) nullUD g36<8,8,1>UD 0x0a0a83b7 urb MsgDesc: 59 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0a83c7 +send(8) nullUD g37<8,8,1>UD 0x0a0a83c7 urb MsgDesc: 60 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0a83d7 +send(8) nullUD g38<8,8,1>UD 0x0a0a83d7 urb MsgDesc: 61 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0a83e7 +send(8) nullUD g39<8,8,1>UD 0x0a0a83e7 urb MsgDesc: 62 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0a83f7 +send(8) nullUD g40<8,8,1>UD 0x0a0a83f7 urb MsgDesc: 63 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x08088027 +send(8) nullUD g11<8,8,1>UD 0x08088027 urb MsgDesc: 2 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x08088037 +send(8) nullUD g12<8,8,1>UD 0x08088037 urb MsgDesc: 3 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x08088047 +send(8) nullUD g13<8,8,1>UD 0x08088047 urb MsgDesc: 4 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x08088057 +send(8) nullUD g14<8,8,1>UD 0x08088057 urb MsgDesc: 5 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x08088067 +send(8) nullUD g15<8,8,1>UD 0x08088067 urb MsgDesc: 6 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x08088077 +send(8) nullUD g16<8,8,1>UD 0x08088077 urb MsgDesc: 7 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x08088087 +send(8) nullUD g17<8,8,1>UD 0x08088087 urb MsgDesc: 8 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x08088097 +send(8) nullUD g18<8,8,1>UD 0x08088097 urb MsgDesc: 9 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080880a7 +send(8) nullUD g19<8,8,1>UD 0x080880a7 urb MsgDesc: 10 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080880b7 +send(8) nullUD g20<8,8,1>UD 0x080880b7 urb MsgDesc: 11 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080880c7 +send(8) nullUD g21<8,8,1>UD 0x080880c7 urb MsgDesc: 12 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080880d7 +send(8) nullUD g22<8,8,1>UD 0x080880d7 urb MsgDesc: 13 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080880e7 +send(8) nullUD g23<8,8,1>UD 0x080880e7 urb MsgDesc: 14 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080880f7 +send(8) nullUD g24<8,8,1>UD 0x080880f7 urb MsgDesc: 15 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x08088107 +send(8) nullUD g25<8,8,1>UD 0x08088107 urb MsgDesc: 16 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x08088117 +send(8) nullUD g26<8,8,1>UD 0x08088117 urb MsgDesc: 17 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x08088127 +send(8) nullUD g27<8,8,1>UD 0x08088127 urb MsgDesc: 18 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x08088137 +send(8) nullUD g28<8,8,1>UD 0x08088137 urb MsgDesc: 19 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x08088147 +send(8) nullUD g29<8,8,1>UD 0x08088147 urb MsgDesc: 20 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x08088157 +send(8) nullUD g30<8,8,1>UD 0x08088157 urb MsgDesc: 21 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x08088167 +send(8) nullUD g31<8,8,1>UD 0x08088167 urb MsgDesc: 22 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x08088177 +send(8) nullUD g32<8,8,1>UD 0x08088177 urb MsgDesc: 23 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x08088187 +send(8) nullUD g33<8,8,1>UD 0x08088187 urb MsgDesc: 24 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x08088197 +send(8) nullUD g34<8,8,1>UD 0x08088197 urb MsgDesc: 25 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080881a7 +send(8) nullUD g35<8,8,1>UD 0x080881a7 urb MsgDesc: 26 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080881b7 +send(8) nullUD g36<8,8,1>UD 0x080881b7 urb MsgDesc: 27 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080881c7 +send(8) nullUD g37<8,8,1>UD 0x080881c7 urb MsgDesc: 28 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080881d7 +send(8) nullUD g38<8,8,1>UD 0x080881d7 urb MsgDesc: 29 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080881e7 +send(8) nullUD g39<8,8,1>UD 0x080881e7 urb MsgDesc: 30 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x080881f7 +send(8) nullUD g40<8,8,1>UD 0x080881f7 urb MsgDesc: 31 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; send(8) g13<1>UD g1<8,8,1>UD 0x02480018 urb MsgDesc: 1 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0c0a0207 +send(8) nullUD g11<8,8,1>UD 0x0c0a0207 urb MsgDesc: 32 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080057 +send(8) nullUD g119<8,8,1>F 0x92080057 urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g10<1>UW g18<8,8,1>UD 0x084a8000 sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; @@ -332,15 +332,15 @@ send(16) g120<1>UW g2<8,8,1>UD 0x08449001 sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; send(16) g32<1>UW g44<8,8,1>UD 0x0865a001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H }; -send(16) null<1>UW g5<8,8,1>UD 0x04008502 +send(16) nullUD g5<8,8,1>UD 0x04008502 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; send(8) g5<1>UW g3<8,8,1>UD 0x02427001 sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; send(16) g8<1>UW g5<8,8,1>UD 0x04847001 sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080007 +send(8) nullUD g119<8,8,1>F 0x92080007 urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g126<8,8,1>UD 0x84080017 +send(8) nullUD g126<8,8,1>UD 0x84080017 urb MsgDesc: 1 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; send(8) g2<1>UW g13<8,8,1>UD 0x0a4b1001 sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; @@ -408,39 +408,39 @@ send(8) g96<1>UD g1<8,8,1>UD 0x021801f8 urb MsgDesc: 31 SIMD8 read mlen 1 rlen 1 { align1 1Q }; send(8) g98<1>UD g1<8,8,1>UD 0x02180208 urb MsgDesc: 32 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0027 +send(8) nullUD g12<8,8,1>UD 0x0c0a0027 urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>UW g126<0,1,0>UD 0x040a02fd +send(8) nullUD g126<0,1,0>UD 0x040a02fd hdc0 MsgDesc: ( DC OWORD block write, 253, 2) mlen 2 rlen 0 { align1 1Q }; send(8) g115<1>UW g115<0,1,0>UD 0x021802fd hdc0 MsgDesc: ( DC OWORD block read, 253, 2) mlen 1 rlen 1 { align1 WE_all 1Q }; -send(8) null<1>F g25<8,8,1>F 0x12080057 +send(8) nullUD g25<8,8,1>F 0x12080057 urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>F 0x12080077 +send(8) nullUD g34<8,8,1>F 0x12080077 urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g43<8,8,1>F 0x12080097 +send(8) nullUD g43<8,8,1>F 0x12080097 urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g52<8,8,1>F 0x120800b7 +send(8) nullUD g52<8,8,1>F 0x120800b7 urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g61<8,8,1>F 0x120800d7 +send(8) nullUD g61<8,8,1>F 0x120800d7 urb MsgDesc: 13 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g70<8,8,1>F 0x120800f7 +send(8) nullUD g70<8,8,1>F 0x120800f7 urb MsgDesc: 15 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080117 +send(8) nullUD g2<8,8,1>F 0x12080117 urb MsgDesc: 17 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080137 +send(8) nullUD g2<8,8,1>F 0x12080137 urb MsgDesc: 19 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080157 +send(8) nullUD g2<8,8,1>F 0x12080157 urb MsgDesc: 21 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g79<8,8,1>F 0x12080177 +send(8) nullUD g79<8,8,1>F 0x12080177 urb MsgDesc: 23 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g88<8,8,1>F 0x12080197 +send(8) nullUD g88<8,8,1>F 0x12080197 urb MsgDesc: 25 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g97<8,8,1>F 0x120801b7 +send(8) nullUD g97<8,8,1>F 0x120801b7 urb MsgDesc: 27 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g106<8,8,1>F 0x120801d7 +send(8) nullUD g106<8,8,1>F 0x120801d7 urb MsgDesc: 29 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g117<8,8,1>F 0x920801f7 +send(8) nullUD g117<8,8,1>F 0x920801f7 urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g11<8,8,1>UD 0x02229001 sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; @@ -448,9 +448,9 @@ send(16) g120<1>UW g11<8,8,1>UD 0x04449001 sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; send(8) g124<1>UW g3<8,8,1>UD 0x08427000 sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) null<1>UW g40<8,8,1>UD 0x04008501 +send(16) nullUD g40<8,8,1>UD 0x04008501 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) null<1>F g127<8,8,1>UD 0x82080007 +send(8) nullUD g127<8,8,1>UD 0x82080007 urb MsgDesc: 0 SIMD8 write mlen 1 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g9<8,8,1>UD 0x0a4a8000 sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; @@ -460,23 +460,23 @@ send(16) g4<1>UW g12<8,8,1>UD 0x0c65a001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; send(8) g2<1>UW g16<8,8,1>UD 0x0e434001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 2Q }; -(+f1.0) send(8) null<1>UW g4<8,8,1>UD 0x02009501 +(+f1.0) send(8) nullUD g4<8,8,1>UD 0x02009501 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; send(8) g6<1>UW g9<8,8,1>UD 0x08434001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) null<1>F g102<8,8,1>F 0x120801f7 +send(8) nullUD g102<8,8,1>F 0x120801f7 urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g121<8,8,1>F 0x8a080217 +send(8) nullUD g121<8,8,1>F 0x8a080217 urb MsgDesc: 33 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(16) null<1>UW g3<0,1,0>UD 0x02008004 +send(16) nullUD g3<0,1,0>UD 0x02008004 gateway MsgDesc: (barrier msg) mlen 1 rlen 0 { align1 WE_all 1H }; send(16) g3<1>UW g14<8,8,1>UD 0x04205efe hdc1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) null<1>F g30<8,8,1>F 0x140a0027 +send(8) nullUD g30<8,8,1>F 0x140a0027 urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>F 0x0c0a0047 +send(8) nullUD g40<8,8,1>F 0x0c0a0047 urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g126<8,8,1>UD 0x84080007 +send(8) nullUD g126<8,8,1>UD 0x84080007 urb MsgDesc: 0 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; send(8) g5<1>UW g11<8,8,1>UD 0x04415001 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; @@ -484,15 +484,15 @@ send(8) g2<1>UW g3<8,8,1>UD 0x04416001 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; send(8) g13<1>UD g3<8,8,1>UD 0x02480038 urb MsgDesc: 3 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g7<8,8,1>F 0x140a0037 +send(8) nullUD g7<8,8,1>F 0x140a0037 urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; send(8) g15<1>UD g2<8,8,1>UD 0x02280038 urb MsgDesc: 3 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080037 +send(8) nullUD g119<8,8,1>F 0x92080037 urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g8<8,8,1>F 0x140a0007 +send(8) nullUD g8<8,8,1>F 0x140a0007 urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0007 +send(8) nullUD g118<8,8,1>F 0x940a0007 urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g12<8,8,1>UD a0<0,1,0>UD 0x00000200 sampler MsgDesc: indirect { align1 1Q }; @@ -514,7 +514,7 @@ send(8) g12<1>UD g2<8,8,1>UD 0x024800b8 urb MsgDesc: 11 SIMD8 read mlen 1 rlen 4 { align1 1Q }; send(8) g7<1>UD g2<8,8,1>UD 0x02480098 urb MsgDesc: 9 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x920800b7 +send(8) nullUD g119<8,8,1>F 0x920800b7 urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g6<1>UW g8<8,8,1>UD 0x084b0000 sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; @@ -546,9 +546,9 @@ send(8) g2<1>UW g19<8,8,1>UD 0x0a4a8001 sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; send(16) g7<1>UW g16<8,8,1>UD 0x128c8001 sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; -send(8) null<1>F g2<8,8,1>F 0x0c0a0057 +send(8) nullUD g2<8,8,1>F 0x0c0a0057 urb MsgDesc: 5 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x04080027 +send(8) nullUD g9<8,8,1>UD 0x04080027 urb MsgDesc: 2 SIMD8 write mlen 2 rlen 0 { align1 1Q }; send(8) g6<1>UW g7<8,8,1>UD 0x08134001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; @@ -556,13 +556,13 @@ send(8) g7<1>UW g11<8,8,1>UD 0x08134102 sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; send(8) g13<1>UW g17<8,8,1>UD 0x021ab000 sampler MsgDesc: sampleinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g50<8,8,1>F 0x140a0057 +send(8) nullUD g50<8,8,1>F 0x140a0057 urb MsgDesc: 5 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g60<8,8,1>F 0x140a0077 +send(8) nullUD g60<8,8,1>F 0x140a0077 urb MsgDesc: 7 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g70<8,8,1>F 0x0c0a0097 +send(8) nullUD g70<8,8,1>F 0x0c0a0097 urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0097 +send(8) nullUD g122<8,8,1>F 0x8c0a0097 urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g6<8,8,1>UD 0x0a4b0000 sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; @@ -574,13 +574,13 @@ send(16) g9<1>UW g11<8,8,1>UD 0x0a2c3001 sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1H }; send(16) g11<1>UW g2<8,8,1>UD 0x0a2c3102 sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 2 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a080077 +send(8) nullUD g123<8,8,1>F 0x8a080077 urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0067 +send(8) nullUD g30<8,8,1>UD 0x0c0a0067 urb MsgDesc: 6 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a0077 +send(8) nullUD g36<8,8,1>UD 0x0c0a0077 urb MsgDesc: 7 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g42<8,8,1>UD 0x0c0a0087 +send(8) nullUD g42<8,8,1>UD 0x0c0a0087 urb MsgDesc: 8 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; send(8) g6<1>UW g6<8,8,1>UD 0x06420102 sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; @@ -660,9 +660,9 @@ send(8) g56<1>UD g2<8,8,1>UD 0x024801e8 urb MsgDesc: 30 SIMD8 read mlen 1 rlen 4 { align1 1Q }; send(8) g57<1>UD g2<8,8,1>UD 0x024801f8 urb MsgDesc: 31 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a8027 +send(8) nullUD g19<8,8,1>UD 0x080a8027 urb MsgDesc: 2 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a0a8027 +send(8) nullUD g8<8,8,1>UD 0x0a0a8027 urb MsgDesc: 2 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; send(8) g6<1>UW g11<8,8,1>UD 0x0e424001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; @@ -672,9 +672,9 @@ send(8) g8<1>UD g14<8,8,1>UD 0x044a0128 urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; send(8) g22<1>UD g16<8,8,1>UD 0x044a0028 urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x0a080017 +send(8) nullUD g6<8,8,1>F 0x0a080017 urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>F 0x0a080057 +send(8) nullUD g7<8,8,1>F 0x0a080057 urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q }; send(8) g4<1>UW g2<8,8,1>UD 0x02406001 hdc1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; @@ -696,11 +696,11 @@ send(8) g5<1>UW g6<8,8,1>UD 0x021ab001 sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; send(16) g6<1>UW g3<8,8,1>UD 0x022cb001 sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0037 +send(8) nullUD g122<8,8,1>F 0x8c0a0037 urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g10<8,8,1>F 0x12080027 +send(8) nullUD g10<8,8,1>F 0x12080027 urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080047 +send(8) nullUD g123<8,8,1>F 0x8a080047 urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g14<1>UW g2<8,8,1>UD 0x04438000 sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; @@ -708,33 +708,33 @@ send(8) g61<1>UD g107<8,8,1>UD 0x02380048 urb MsgDesc: 4 SIMD8 read mlen 1 rlen 3 { align1 1Q }; send(8) g64<1>UD g113<8,8,1>UD 0x02380058 urb MsgDesc: 5 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080047 +send(8) nullUD g119<8,8,1>F 0x92080047 urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g5<1>UW g4<8,8,1>UD 0x06415001 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q }; send(8) g2<1>UW g10<8,8,1>UD 0x06416001 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q }; -send(8) null<1>F g119<8,8,1>F 0x92080077 +send(8) nullUD g119<8,8,1>F 0x92080077 urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g12<1>UD g8<4,4,1>UD 0x044a0038 urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; send(8) g21<1>UD g8<4,4,1>UD 0x044a0048 urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a00a7 +send(8) nullUD g22<8,8,1>UD 0x0c0a00a7 urb MsgDesc: 10 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; send(16) g1<1>UW g9<8,8,1>UD 0x08858001 sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) null<1>F g56<8,8,1>F 0x140a0097 +send(8) nullUD g56<8,8,1>F 0x140a0097 urb MsgDesc: 9 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g76<8,8,1>F 0x0c0a00b7 +send(8) nullUD g76<8,8,1>F 0x0c0a00b7 urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a00b7 +send(8) nullUD g122<8,8,1>F 0x8c0a00b7 urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g4<1>UW g3<8,8,1>UD 0x0232a001 sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; send(16) g8<1>UW g3<8,8,1>UD 0x0464a001 sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H }; -send(8) null<1>F g6<8,8,1>UD 0x0a080007 +send(8) nullUD g6<8,8,1>UD 0x0a080007 urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q }; send(8) g126<1>UW g10<8,8,1>UD 0x08123001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; @@ -760,7 +760,7 @@ send(8) g2<1>UW g15<8,8,1>UD 0x06422001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; send(16) g14<1>UW g8<8,8,1>UD 0x0c842001 sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(8) null<1>F g118<8,8,1>F 0x940a0037 +send(8) nullUD g118<8,8,1>F 0x940a0037 urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; send(8) g4<1>UW g5<8,8,1>UD 0x0212a001 sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; @@ -788,67 +788,67 @@ send(8) g8<1>UD g35<8,8,1>UD 0x02480428 urb MsgDesc: 66 SIMD8 read mlen 1 rlen 4 { align1 1Q }; send(8) g12<1>UD g35<8,8,1>UD 0x02480628 urb MsgDesc: 98 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a0a8037 +send(8) nullUD g6<8,8,1>UD 0x0a0a8037 urb MsgDesc: 3 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0a0a8047 +send(8) nullUD g11<8,8,1>UD 0x0a0a8047 urb MsgDesc: 4 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0a0a8057 +send(8) nullUD g12<8,8,1>UD 0x0a0a8057 urb MsgDesc: 5 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0a0a8067 +send(8) nullUD g13<8,8,1>UD 0x0a0a8067 urb MsgDesc: 6 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0a0a8077 +send(8) nullUD g14<8,8,1>UD 0x0a0a8077 urb MsgDesc: 7 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0a0a8087 +send(8) nullUD g15<8,8,1>UD 0x0a0a8087 urb MsgDesc: 8 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a0a8097 +send(8) nullUD g16<8,8,1>UD 0x0a0a8097 urb MsgDesc: 9 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a0a80a7 +send(8) nullUD g17<8,8,1>UD 0x0a0a80a7 urb MsgDesc: 10 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a0a80b7 +send(8) nullUD g18<8,8,1>UD 0x0a0a80b7 urb MsgDesc: 11 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a0a80c7 +send(8) nullUD g19<8,8,1>UD 0x0a0a80c7 urb MsgDesc: 12 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0a80d7 +send(8) nullUD g20<8,8,1>UD 0x0a0a80d7 urb MsgDesc: 13 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0a80e7 +send(8) nullUD g21<8,8,1>UD 0x0a0a80e7 urb MsgDesc: 14 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0a80f7 +send(8) nullUD g22<8,8,1>UD 0x0a0a80f7 urb MsgDesc: 15 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0a8107 +send(8) nullUD g23<8,8,1>UD 0x0a0a8107 urb MsgDesc: 16 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0a8117 +send(8) nullUD g24<8,8,1>UD 0x0a0a8117 urb MsgDesc: 17 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0a8127 +send(8) nullUD g25<8,8,1>UD 0x0a0a8127 urb MsgDesc: 18 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a0a8137 +send(8) nullUD g26<8,8,1>UD 0x0a0a8137 urb MsgDesc: 19 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a0a8147 +send(8) nullUD g27<8,8,1>UD 0x0a0a8147 urb MsgDesc: 20 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a0a8157 +send(8) nullUD g28<8,8,1>UD 0x0a0a8157 urb MsgDesc: 21 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a0a8167 +send(8) nullUD g29<8,8,1>UD 0x0a0a8167 urb MsgDesc: 22 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a0a8177 +send(8) nullUD g30<8,8,1>UD 0x0a0a8177 urb MsgDesc: 23 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a0a8187 +send(8) nullUD g31<8,8,1>UD 0x0a0a8187 urb MsgDesc: 24 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a0a8197 +send(8) nullUD g32<8,8,1>UD 0x0a0a8197 urb MsgDesc: 25 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a0a81a7 +send(8) nullUD g33<8,8,1>UD 0x0a0a81a7 urb MsgDesc: 26 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a0a81b7 +send(8) nullUD g34<8,8,1>UD 0x0a0a81b7 urb MsgDesc: 27 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a0a81c7 +send(8) nullUD g35<8,8,1>UD 0x0a0a81c7 urb MsgDesc: 28 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0a81d7 +send(8) nullUD g36<8,8,1>UD 0x0a0a81d7 urb MsgDesc: 29 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0a81e7 +send(8) nullUD g37<8,8,1>UD 0x0a0a81e7 urb MsgDesc: 30 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0a81f7 +send(8) nullUD g38<8,8,1>UD 0x0a0a81f7 urb MsgDesc: 31 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0a8207 +send(8) nullUD g39<8,8,1>UD 0x0a0a8207 urb MsgDesc: 32 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0027 +send(8) nullUD g122<8,8,1>F 0x8c0a0027 urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g2<8,8,1>UD 0x06424001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; @@ -866,25 +866,25 @@ send(8) g4<1>UW g5<8,8,1>UD 0x04120001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; send(16) g4<1>UW g7<8,8,1>UD 0x08240001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(8) null<1>F g118<8,8,1>F 0x940a0027 +send(8) nullUD g118<8,8,1>F 0x940a0027 urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g2<8,8,1>F 0x12080067 +send(8) nullUD g2<8,8,1>F 0x12080067 urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080087 +send(8) nullUD g123<8,8,1>F 0x8a080087 urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g21<1>UD g2<8,8,1>UD 0x02380068 urb MsgDesc: 6 SIMD8 read mlen 1 rlen 3 { align1 1Q }; send(8) g35<1>UD g2<8,8,1>UD 0x02380088 urb MsgDesc: 8 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g5<8,8,1>F 0x140a0067 +send(8) nullUD g5<8,8,1>F 0x140a0067 urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0067 +send(8) nullUD g118<8,8,1>F 0x940a0067 urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; send(8) g2<1>UW g8<8,8,1>UD 0x04220001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; send(16) g2<1>UW g14<8,8,1>UD 0x08440001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a0800d7 +send(8) nullUD g123<8,8,1>F 0x8a0800d7 urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g22<1>UW g14<8,8,1>UD 0x064a8405 sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; @@ -904,7 +904,7 @@ send(16) g10<1>UW g26<8,8,1>UD 0x128c8304 sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 9 rlen 8 { align1 1H }; send(8) g6<1>UW g15<8,8,1>UD 0x0e4a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; -send(16) null<1>UW g2<8,8,1>UD 0x04008601 +send(16) nullUD g2<8,8,1>UD 0x04008601 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H }; send(8) g124<1>UW g2<8,8,1>UD 0x08422001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; @@ -918,7 +918,7 @@ send(16) g10<1>UW g12<8,8,1>UD 0x10246001 sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; send(16) g12<1>UW g20<8,8,1>UD 0x10246102 sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; -send(8) null<1>F g18<8,8,1>UD 0x0e0a8047 +send(8) nullUD g18<8,8,1>UD 0x0e0a8047 urb MsgDesc: 4 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(8) g9<1>UD g34<8,8,1>UD 0x02480218 urb MsgDesc: 33 SIMD8 read mlen 1 rlen 4 { align1 1Q }; @@ -928,65 +928,65 @@ send(8) g2<1>UD g6<8,8,1>UD 0x041a0128 urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; send(8) g22<1>UD g8<8,8,1>UD 0x041a0028 urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) null<1>F g2<8,8,1>UD 0x06088027 +send(8) nullUD g2<8,8,1>UD 0x06088027 urb MsgDesc: 2 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x06088037 +send(8) nullUD g12<8,8,1>UD 0x06088037 urb MsgDesc: 3 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x06088047 +send(8) nullUD g13<8,8,1>UD 0x06088047 urb MsgDesc: 4 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x06088057 +send(8) nullUD g14<8,8,1>UD 0x06088057 urb MsgDesc: 5 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x06088067 +send(8) nullUD g15<8,8,1>UD 0x06088067 urb MsgDesc: 6 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x06088077 +send(8) nullUD g16<8,8,1>UD 0x06088077 urb MsgDesc: 7 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x06088087 +send(8) nullUD g17<8,8,1>UD 0x06088087 urb MsgDesc: 8 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x06088097 +send(8) nullUD g18<8,8,1>UD 0x06088097 urb MsgDesc: 9 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x060880a7 +send(8) nullUD g19<8,8,1>UD 0x060880a7 urb MsgDesc: 10 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x060880b7 +send(8) nullUD g20<8,8,1>UD 0x060880b7 urb MsgDesc: 11 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x060880c7 +send(8) nullUD g21<8,8,1>UD 0x060880c7 urb MsgDesc: 12 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x060880d7 +send(8) nullUD g22<8,8,1>UD 0x060880d7 urb MsgDesc: 13 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x060880e7 +send(8) nullUD g23<8,8,1>UD 0x060880e7 urb MsgDesc: 14 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x060880f7 +send(8) nullUD g24<8,8,1>UD 0x060880f7 urb MsgDesc: 15 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x06088107 +send(8) nullUD g25<8,8,1>UD 0x06088107 urb MsgDesc: 16 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x06088117 +send(8) nullUD g26<8,8,1>UD 0x06088117 urb MsgDesc: 17 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x06088127 +send(8) nullUD g27<8,8,1>UD 0x06088127 urb MsgDesc: 18 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x06088137 +send(8) nullUD g28<8,8,1>UD 0x06088137 urb MsgDesc: 19 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x06088147 +send(8) nullUD g29<8,8,1>UD 0x06088147 urb MsgDesc: 20 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x06088157 +send(8) nullUD g30<8,8,1>UD 0x06088157 urb MsgDesc: 21 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x06088167 +send(8) nullUD g31<8,8,1>UD 0x06088167 urb MsgDesc: 22 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x06088177 +send(8) nullUD g32<8,8,1>UD 0x06088177 urb MsgDesc: 23 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x06088187 +send(8) nullUD g33<8,8,1>UD 0x06088187 urb MsgDesc: 24 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x06088197 +send(8) nullUD g34<8,8,1>UD 0x06088197 urb MsgDesc: 25 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x060881a7 +send(8) nullUD g35<8,8,1>UD 0x060881a7 urb MsgDesc: 26 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x060881b7 +send(8) nullUD g36<8,8,1>UD 0x060881b7 urb MsgDesc: 27 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x060881c7 +send(8) nullUD g37<8,8,1>UD 0x060881c7 urb MsgDesc: 28 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x060881d7 +send(8) nullUD g38<8,8,1>UD 0x060881d7 urb MsgDesc: 29 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x060881e7 +send(8) nullUD g39<8,8,1>UD 0x060881e7 urb MsgDesc: 30 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x060881f7 +send(8) nullUD g40<8,8,1>UD 0x060881f7 urb MsgDesc: 31 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; send(8) g3<1>UW g10<8,8,1>UD 0x0242a001 sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; @@ -1006,9 +1006,9 @@ send(8) g23<1>UW g2<8,8,1>UD 0x04115e01 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; send(8) g39<1>UW g45<8,8,1>UD 0x04116e01 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q }; -(+f1.0) send(8) null<1>UW g2<8,8,1>UD 0x04018501 +(+f1.0) send(8) nullUD g2<8,8,1>UD 0x04018501 hdc1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1Q }; -(+f1.0) send(8) null<1>UW g42<8,8,1>UD 0x04019501 +(+f1.0) send(8) nullUD g42<8,8,1>UD 0x04019501 hdc1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 0 { align1 2Q }; send(8) g2<1>UW g6<8,8,1>UD 0x04423001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; @@ -1034,119 +1034,119 @@ send(8) g21<1>UD g29<8,8,1>UD 0x044a0618 urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; send(8) g25<1>UD g29<8,8,1>UD 0x044a0818 urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c0a0217 +send(8) nullUD g6<8,8,1>UD 0x0c0a0217 urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0227 +send(8) nullUD g12<8,8,1>UD 0x0c0a0227 urb MsgDesc: 34 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0c0a0237 +send(8) nullUD g13<8,8,1>UD 0x0c0a0237 urb MsgDesc: 35 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a0247 +send(8) nullUD g14<8,8,1>UD 0x0c0a0247 urb MsgDesc: 36 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a0257 +send(8) nullUD g15<8,8,1>UD 0x0c0a0257 urb MsgDesc: 37 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a0267 +send(8) nullUD g16<8,8,1>UD 0x0c0a0267 urb MsgDesc: 38 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a0277 +send(8) nullUD g17<8,8,1>UD 0x0c0a0277 urb MsgDesc: 39 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a0287 +send(8) nullUD g18<8,8,1>UD 0x0c0a0287 urb MsgDesc: 40 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a0297 +send(8) nullUD g19<8,8,1>UD 0x0c0a0297 urb MsgDesc: 41 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a02a7 +send(8) nullUD g20<8,8,1>UD 0x0c0a02a7 urb MsgDesc: 42 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a02b7 +send(8) nullUD g21<8,8,1>UD 0x0c0a02b7 urb MsgDesc: 43 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a02c7 +send(8) nullUD g22<8,8,1>UD 0x0c0a02c7 urb MsgDesc: 44 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a02d7 +send(8) nullUD g23<8,8,1>UD 0x0c0a02d7 urb MsgDesc: 45 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a02e7 +send(8) nullUD g24<8,8,1>UD 0x0c0a02e7 urb MsgDesc: 46 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a02f7 +send(8) nullUD g25<8,8,1>UD 0x0c0a02f7 urb MsgDesc: 47 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a0307 +send(8) nullUD g26<8,8,1>UD 0x0c0a0307 urb MsgDesc: 48 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a0317 +send(8) nullUD g27<8,8,1>UD 0x0c0a0317 urb MsgDesc: 49 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a0327 +send(8) nullUD g28<8,8,1>UD 0x0c0a0327 urb MsgDesc: 50 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a0337 +send(8) nullUD g29<8,8,1>UD 0x0c0a0337 urb MsgDesc: 51 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0347 +send(8) nullUD g30<8,8,1>UD 0x0c0a0347 urb MsgDesc: 52 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a0357 +send(8) nullUD g31<8,8,1>UD 0x0c0a0357 urb MsgDesc: 53 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a0367 +send(8) nullUD g32<8,8,1>UD 0x0c0a0367 urb MsgDesc: 54 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a0377 +send(8) nullUD g33<8,8,1>UD 0x0c0a0377 urb MsgDesc: 55 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a0387 +send(8) nullUD g34<8,8,1>UD 0x0c0a0387 urb MsgDesc: 56 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a0397 +send(8) nullUD g35<8,8,1>UD 0x0c0a0397 urb MsgDesc: 57 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a03a7 +send(8) nullUD g36<8,8,1>UD 0x0c0a03a7 urb MsgDesc: 58 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a03b7 +send(8) nullUD g37<8,8,1>UD 0x0c0a03b7 urb MsgDesc: 59 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a03c7 +send(8) nullUD g38<8,8,1>UD 0x0c0a03c7 urb MsgDesc: 60 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a03d7 +send(8) nullUD g39<8,8,1>UD 0x0c0a03d7 urb MsgDesc: 61 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a03e7 +send(8) nullUD g40<8,8,1>UD 0x0c0a03e7 urb MsgDesc: 62 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a03f7 +send(8) nullUD g41<8,8,1>UD 0x0c0a03f7 urb MsgDesc: 63 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a080067 +send(8) nullUD g16<8,8,1>UD 0x0a080067 urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a080077 +send(8) nullUD g17<8,8,1>UD 0x0a080077 urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a080087 +send(8) nullUD g18<8,8,1>UD 0x0a080087 urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a080097 +send(8) nullUD g19<8,8,1>UD 0x0a080097 urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0800a7 +send(8) nullUD g20<8,8,1>UD 0x0a0800a7 urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0800b7 +send(8) nullUD g21<8,8,1>UD 0x0a0800b7 urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0800c7 +send(8) nullUD g22<8,8,1>UD 0x0a0800c7 urb MsgDesc: 12 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0800d7 +send(8) nullUD g23<8,8,1>UD 0x0a0800d7 urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0800e7 +send(8) nullUD g24<8,8,1>UD 0x0a0800e7 urb MsgDesc: 14 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0800f7 +send(8) nullUD g25<8,8,1>UD 0x0a0800f7 urb MsgDesc: 15 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a080107 +send(8) nullUD g26<8,8,1>UD 0x0a080107 urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a080117 +send(8) nullUD g27<8,8,1>UD 0x0a080117 urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a080127 +send(8) nullUD g28<8,8,1>UD 0x0a080127 urb MsgDesc: 18 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a080137 +send(8) nullUD g29<8,8,1>UD 0x0a080137 urb MsgDesc: 19 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a080147 +send(8) nullUD g30<8,8,1>UD 0x0a080147 urb MsgDesc: 20 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a080157 +send(8) nullUD g31<8,8,1>UD 0x0a080157 urb MsgDesc: 21 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a080167 +send(8) nullUD g32<8,8,1>UD 0x0a080167 urb MsgDesc: 22 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a080177 +send(8) nullUD g33<8,8,1>UD 0x0a080177 urb MsgDesc: 23 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a080187 +send(8) nullUD g34<8,8,1>UD 0x0a080187 urb MsgDesc: 24 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a080197 +send(8) nullUD g35<8,8,1>UD 0x0a080197 urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0801a7 +send(8) nullUD g36<8,8,1>UD 0x0a0801a7 urb MsgDesc: 26 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0801b7 +send(8) nullUD g37<8,8,1>UD 0x0a0801b7 urb MsgDesc: 27 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0801c7 +send(8) nullUD g38<8,8,1>UD 0x0a0801c7 urb MsgDesc: 28 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0801d7 +send(8) nullUD g39<8,8,1>UD 0x0a0801d7 urb MsgDesc: 29 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0801e7 +send(8) nullUD g40<8,8,1>UD 0x0a0801e7 urb MsgDesc: 30 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0a0801f7 +send(8) nullUD g41<8,8,1>UD 0x0a0801f7 urb MsgDesc: 31 SIMD8 write mlen 5 rlen 0 { align1 1Q }; send(8) g13<1>UW g2<8,8,1>UD 0x06123001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; @@ -1162,15 +1162,15 @@ send(16) g7<1>UW g27<8,8,1>UD 0x08840203 sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H }; send(16) g4<1>UW g17<8,8,1>UD 0x0420a503 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g18<8,8,1>UD 0x04008504 +send(16) nullUD g18<8,8,1>UD 0x04008504 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 4, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; send(16) g11<1>UW g19<8,8,1>UD 0x0420a602 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g20<8,8,1>UD 0x04008505 +send(16) nullUD g20<8,8,1>UD 0x04008505 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 5, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; send(16) g16<1>UW g21<8,8,1>UD 0x04205e01 hdc1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g22<8,8,1>UD 0x04008506 +send(16) nullUD g22<8,8,1>UD 0x04008506 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 6, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; send(8) g26<1>UW g26<8,8,1>UD 0x0242a203 sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; @@ -1220,9 +1220,9 @@ send(16) g66<1>UW g74<8,8,1>UD 0x0484a809 sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H }; send(16) g74<1>UW g108<8,8,1>UD 0x0484a90a sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H }; -send(16) null<1>UW g3<8,8,1>UD 0x040085fe +send(16) nullUD g3<8,8,1>UD 0x040085fe hdc1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080067 +send(8) nullUD g119<8,8,1>F 0x92080067 urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g6<1>UW g20<8,8,1>UD 0x12424001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q }; @@ -1232,11 +1232,11 @@ send(16) g2<1>UW g7<8,8,1>UD 0x0825a001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; send(8) g9<1>UW g17<8,8,1>UD 0x06422000 sampler MsgDesc: sample_l SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) null<1>UW g123<0,1,0>UD 0x060a03fd +send(16) nullUD g123<0,1,0>UD 0x060a03fd hdc0 MsgDesc: ( DC OWORD block write, 253, 3) mlen 3 rlen 0 { align1 1H }; send(16) g114<1>UW g114<0,1,0>UD 0x022803fd hdc0 MsgDesc: ( DC OWORD block read, 253, 3) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0127 +send(8) nullUD g12<8,8,1>UD 0x0c0a0127 urb MsgDesc: 18 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; send(8) g2<1>UW g11<8,8,1>UD 0x04420405 sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; @@ -1362,11 +1362,11 @@ send(16) g10<1>UW g4<8,8,1>UD 0x04440102 sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1H }; send(16) g14<1>UW g6<8,8,1>UD 0x04640102 sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 6 { align1 1H }; -send(8) null<1>F g8<8,8,1>UD 0x0c0a8027 +send(8) nullUD g8<8,8,1>UD 0x0c0a8027 urb MsgDesc: 2 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>F 0x12080047 +send(8) nullUD g13<8,8,1>F 0x12080047 urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080087 +send(8) nullUD g119<8,8,1>F 0x92080087 urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g5<1>UW g10<8,8,1>UD 0x06420001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; @@ -1376,7 +1376,7 @@ send(8) g1<1>UW g125<8,8,1>UD 0x02106e02 hdc1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; send(8) g8<1>UW g22<8,8,1>UD 0x02106efe hdc1 MsgDesc: ( untyped surface read, Surface = 254, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080097 +send(8) nullUD g123<8,8,1>F 0x8a080097 urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g29<1>UW g5<8,8,1>UD 0x0e4b2001 sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; @@ -1396,11 +1396,11 @@ send(8) g125<1>UW g5<8,8,1>UD 0x04220102 sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1Q }; send(16) g122<1>UW g7<8,8,1>UD 0x08440102 sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1H }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8037 +send(8) nullUD g14<8,8,1>UD 0x0c0a8037 urb MsgDesc: 3 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8047 +send(8) nullUD g15<8,8,1>UD 0x0c0a8047 urb MsgDesc: 4 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8057 +send(8) nullUD g16<8,8,1>UD 0x0c0a8057 urb MsgDesc: 5 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; send(8) g6<1>UW g7<8,8,1>UD 0x081a5001 sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; @@ -1460,15 +1460,15 @@ send(16) g77<1>UW g2<8,8,1>UD 0x0885a70f sampler MsgDesc: ld_lz SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; send(16) g83<1>UW g86<8,8,1>UD 0x04205e00 hdc1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0047 +send(8) nullUD g122<8,8,1>F 0x8c0a0047 urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g14<1>UW g11<8,8,1>UD 0x084b0202 sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; send(8) g6<1>UW g6<8,8,1>UD 0x0a4b0101 sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; -send(8) null<1>F g3<8,8,1>F 0x12080087 +send(8) nullUD g3<8,8,1>F 0x12080087 urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a0800a7 +send(8) nullUD g123<8,8,1>F 0x8a0800a7 urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g6<1>UW g7<8,8,1>UD 0x081a6001 sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; @@ -1668,73 +1668,73 @@ send(8) g14<1>UD g60<8,8,1>UD 0x02380618 urb MsgDesc: 97 SIMD8 read mlen 1 rlen 3 { align1 1Q }; send(8) g17<1>UD g60<8,8,1>UD 0x02380818 urb MsgDesc: 129 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8067 +send(8) nullUD g14<8,8,1>UD 0x0c0a8067 urb MsgDesc: 6 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8077 +send(8) nullUD g15<8,8,1>UD 0x0c0a8077 urb MsgDesc: 7 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8087 +send(8) nullUD g16<8,8,1>UD 0x0c0a8087 urb MsgDesc: 8 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a8097 +send(8) nullUD g17<8,8,1>UD 0x0c0a8097 urb MsgDesc: 9 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a80a7 +send(8) nullUD g18<8,8,1>UD 0x0c0a80a7 urb MsgDesc: 10 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a80b7 +send(8) nullUD g19<8,8,1>UD 0x0c0a80b7 urb MsgDesc: 11 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a80c7 +send(8) nullUD g20<8,8,1>UD 0x0c0a80c7 urb MsgDesc: 12 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a80d7 +send(8) nullUD g21<8,8,1>UD 0x0c0a80d7 urb MsgDesc: 13 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a80e7 +send(8) nullUD g22<8,8,1>UD 0x0c0a80e7 urb MsgDesc: 14 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a80f7 +send(8) nullUD g23<8,8,1>UD 0x0c0a80f7 urb MsgDesc: 15 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a8107 +send(8) nullUD g24<8,8,1>UD 0x0c0a8107 urb MsgDesc: 16 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a8117 +send(8) nullUD g25<8,8,1>UD 0x0c0a8117 urb MsgDesc: 17 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a8127 +send(8) nullUD g26<8,8,1>UD 0x0c0a8127 urb MsgDesc: 18 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a8137 +send(8) nullUD g27<8,8,1>UD 0x0c0a8137 urb MsgDesc: 19 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a8147 +send(8) nullUD g28<8,8,1>UD 0x0c0a8147 urb MsgDesc: 20 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a8157 +send(8) nullUD g29<8,8,1>UD 0x0c0a8157 urb MsgDesc: 21 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a8167 +send(8) nullUD g30<8,8,1>UD 0x0c0a8167 urb MsgDesc: 22 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a8177 +send(8) nullUD g31<8,8,1>UD 0x0c0a8177 urb MsgDesc: 23 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a8187 +send(8) nullUD g32<8,8,1>UD 0x0c0a8187 urb MsgDesc: 24 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a8197 +send(8) nullUD g33<8,8,1>UD 0x0c0a8197 urb MsgDesc: 25 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a81a7 +send(8) nullUD g34<8,8,1>UD 0x0c0a81a7 urb MsgDesc: 26 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a81b7 +send(8) nullUD g35<8,8,1>UD 0x0c0a81b7 urb MsgDesc: 27 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a81c7 +send(8) nullUD g36<8,8,1>UD 0x0c0a81c7 urb MsgDesc: 28 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a81d7 +send(8) nullUD g37<8,8,1>UD 0x0c0a81d7 urb MsgDesc: 29 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a81e7 +send(8) nullUD g38<8,8,1>UD 0x0c0a81e7 urb MsgDesc: 30 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a81f7 +send(8) nullUD g39<8,8,1>UD 0x0c0a81f7 urb MsgDesc: 31 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a8207 +send(8) nullUD g40<8,8,1>UD 0x0c0a8207 urb MsgDesc: 32 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a8217 +send(8) nullUD g41<8,8,1>UD 0x0c0a8217 urb MsgDesc: 33 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; send(8) g124<1>UW g2<8,8,1>UD 0x02106e01 hdc1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; send(16) g11<1>UW g19<8,8,1>UD 0x0420a601 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g20<8,8,1>UD 0x04008503 +send(16) nullUD g20<8,8,1>UD 0x04008503 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; send(8) g17<1>UW g11<8,8,1>UD 0x0813e001 sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; send(16) g22<1>UW g2<8,8,1>UD 0x1025e001 sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>UD 0x8c088007 +send(8) nullUD g122<8,8,1>UD 0x8c088007 urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q EOT }; send(8) g2<1>UW g2<8,8,1>UD 0x06423001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; @@ -1764,7 +1764,7 @@ send(16) g2<1>UW g15<8,8,1>UD 0x04840001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; send(8) g7<1>UW g44<8,8,1>UD 0x02106e00 hdc1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>UW g44<8,8,1>UD 0x02009500 +send(8) nullUD g44<8,8,1>UD 0x02009500 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; send(8) g7<1>UD g37<8,8,1>UD 0x02480438 urb MsgDesc: 67 SIMD8 read mlen 1 rlen 4 { align1 1Q }; @@ -1822,59 +1822,59 @@ send(8) g42<1>UW g64<8,8,1>UD 0x0242700d sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; send(8) g124<1>UW g6<8,8,1>UD 0x04438505 sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a088067 +send(8) nullUD g16<8,8,1>UD 0x0a088067 urb MsgDesc: 6 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a088077 +send(8) nullUD g17<8,8,1>UD 0x0a088077 urb MsgDesc: 7 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a088087 +send(8) nullUD g18<8,8,1>UD 0x0a088087 urb MsgDesc: 8 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a088097 +send(8) nullUD g19<8,8,1>UD 0x0a088097 urb MsgDesc: 9 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0880a7 +send(8) nullUD g20<8,8,1>UD 0x0a0880a7 urb MsgDesc: 10 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0880b7 +send(8) nullUD g21<8,8,1>UD 0x0a0880b7 urb MsgDesc: 11 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0880c7 +send(8) nullUD g22<8,8,1>UD 0x0a0880c7 urb MsgDesc: 12 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0880d7 +send(8) nullUD g23<8,8,1>UD 0x0a0880d7 urb MsgDesc: 13 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0880e7 +send(8) nullUD g24<8,8,1>UD 0x0a0880e7 urb MsgDesc: 14 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0880f7 +send(8) nullUD g25<8,8,1>UD 0x0a0880f7 urb MsgDesc: 15 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a088107 +send(8) nullUD g26<8,8,1>UD 0x0a088107 urb MsgDesc: 16 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a088117 +send(8) nullUD g27<8,8,1>UD 0x0a088117 urb MsgDesc: 17 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a088127 +send(8) nullUD g28<8,8,1>UD 0x0a088127 urb MsgDesc: 18 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a088137 +send(8) nullUD g29<8,8,1>UD 0x0a088137 urb MsgDesc: 19 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a088147 +send(8) nullUD g30<8,8,1>UD 0x0a088147 urb MsgDesc: 20 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a088157 +send(8) nullUD g31<8,8,1>UD 0x0a088157 urb MsgDesc: 21 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a088167 +send(8) nullUD g32<8,8,1>UD 0x0a088167 urb MsgDesc: 22 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a088177 +send(8) nullUD g33<8,8,1>UD 0x0a088177 urb MsgDesc: 23 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a088187 +send(8) nullUD g34<8,8,1>UD 0x0a088187 urb MsgDesc: 24 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a088197 +send(8) nullUD g35<8,8,1>UD 0x0a088197 urb MsgDesc: 25 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0881a7 +send(8) nullUD g36<8,8,1>UD 0x0a0881a7 urb MsgDesc: 26 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0881b7 +send(8) nullUD g37<8,8,1>UD 0x0a0881b7 urb MsgDesc: 27 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0881c7 +send(8) nullUD g38<8,8,1>UD 0x0a0881c7 urb MsgDesc: 28 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0881d7 +send(8) nullUD g39<8,8,1>UD 0x0a0881d7 urb MsgDesc: 29 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0881e7 +send(8) nullUD g40<8,8,1>UD 0x0a0881e7 urb MsgDesc: 30 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0a0881f7 +send(8) nullUD g41<8,8,1>UD 0x0a0881f7 urb MsgDesc: 31 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g4<8,8,1>UD 0x0e0a8027 +send(8) nullUD g4<8,8,1>UD 0x0e0a8027 urb MsgDesc: 2 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(8) g5<1>UW g6<8,8,1>UD 0x04123001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; @@ -1920,15 +1920,15 @@ send(8) g124<1>UW g6<8,8,1>UD 0x04338000 sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; send(8) g12<1>UD g1<8,8,1>UD 0x02280058 urb MsgDesc: 5 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a8067 +send(8) nullUD g12<8,8,1>UD 0x0e0a8067 urb MsgDesc: 6 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(8) g12<1>UD g1<8,8,1>UD 0x02280078 urb MsgDesc: 7 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a8087 +send(8) nullUD g12<8,8,1>UD 0x0e0a8087 urb MsgDesc: 8 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(8) g12<1>UD g1<8,8,1>UD 0x02280098 urb MsgDesc: 9 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a80a7 +send(8) nullUD g12<8,8,1>UD 0x0e0a80a7 urb MsgDesc: 10 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(16) g9<1>UW g17<8,8,1>UD 0x04847002 sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H }; @@ -2012,13 +2012,13 @@ send(16) g12<1>UW g48<8,8,1>UD 0x08640405 sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 6 { align1 1H }; send(16) g38<1>UW g44<8,8,1>UD 0x08640304 sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 6 { align1 1H }; -(+f1.0) send(8) null<1>UW g94<8,8,1>UD 0x02009601 +(+f1.0) send(8) nullUD g94<8,8,1>UD 0x02009601 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; (+f1.0) send(8) g47<1>UW g94<8,8,1>UD 0x0210b601 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; send(16) g4<1>UW g1<8,8,1>UD 0x04405c02 hdc1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xc) mlen 2 rlen 4 { align1 1H }; -send(8) null<1>UW g100<8,8,1>UD 0x02009600 +send(8) nullUD g100<8,8,1>UD 0x02009600 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; send(8) g51<1>UW g100<8,8,1>UD 0x0210b600 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; @@ -2026,7 +2026,7 @@ send(8) g5<1>UW g11<8,8,1>UD 0x064a0001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; send(16) g7<1>UW g19<8,8,1>UD 0x0a8c0001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a080117 +send(8) nullUD g123<8,8,1>F 0x8a080117 urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g3<1>UW g3<8,8,1>UD 0x02415002 hdc1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; @@ -2034,13 +2034,13 @@ send(8) g5<1>UW g4<8,8,1>UD 0x02416002 hdc1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q }; send(8) g6<1>UW g16<8,8,1>UD 0x0210b500 hdc1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080097 +send(8) nullUD g119<8,8,1>F 0x92080097 urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g4<8,8,1>F 0x120800c7 +send(8) nullUD g4<8,8,1>F 0x120800c7 urb MsgDesc: 12 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g5<8,8,1>F 0x120800e7 +send(8) nullUD g5<8,8,1>F 0x120800e7 urb MsgDesc: 14 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080107 +send(8) nullUD g123<8,8,1>F 0x8a080107 urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g6<1>UW g11<8,8,1>UD 0x08434102 sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; @@ -2082,35 +2082,35 @@ send(8) g13<1>UD g1<8,8,1>UD 0x02380108 urb MsgDesc: 16 SIMD8 read mlen 1 rlen 3 { align1 1Q }; send(8) g13<1>UD g1<8,8,1>UD 0x02380118 urb MsgDesc: 17 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g60<8,8,1>F 0x120800a7 +send(8) nullUD g60<8,8,1>F 0x120800a7 urb MsgDesc: 10 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080107 +send(8) nullUD g119<8,8,1>F 0x92080107 urb MsgDesc: 16 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; send(8) g3<1>UW g7<8,8,1>UD 0x02115e01 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; send(8) g5<1>UW g11<8,8,1>UD 0x02116e01 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 2Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080067 +send(8) nullUD g123<8,8,1>F 0x8a080067 urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g80<8,8,1>F 0x140a00b7 +send(8) nullUD g80<8,8,1>F 0x140a00b7 urb MsgDesc: 11 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a00d7 +send(8) nullUD g6<8,8,1>F 0x140a00d7 urb MsgDesc: 13 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a00f7 +send(8) nullUD g6<8,8,1>F 0x140a00f7 urb MsgDesc: 15 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0117 +send(8) nullUD g6<8,8,1>F 0x140a0117 urb MsgDesc: 17 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0137 +send(8) nullUD g6<8,8,1>F 0x140a0137 urb MsgDesc: 19 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g90<8,8,1>F 0x140a0157 +send(8) nullUD g90<8,8,1>F 0x140a0157 urb MsgDesc: 21 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g100<8,8,1>F 0x140a0177 +send(8) nullUD g100<8,8,1>F 0x140a0177 urb MsgDesc: 23 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g110<8,8,1>F 0x0c0a0197 +send(8) nullUD g110<8,8,1>F 0x0c0a0197 urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0197 +send(8) nullUD g120<8,8,1>F 0x8c0a0197 urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g123<8,8,1>F 0x8a0800b7 +send(8) nullUD g123<8,8,1>F 0x8a0800b7 urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g22<1>UD g53<8,8,1>UD 0x02180238 urb MsgDesc: 35 SIMD8 read mlen 1 rlen 1 { align1 1Q }; @@ -2300,67 +2300,67 @@ send(8) g37<1>UD g22<8,8,1>UD 0x02180618 urb MsgDesc: 97 SIMD8 read mlen 1 rlen 1 { align1 1Q }; send(8) g38<1>UD g22<8,8,1>UD 0x02180818 urb MsgDesc: 129 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x080a8037 +send(8) nullUD g6<8,8,1>UD 0x080a8037 urb MsgDesc: 3 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x080a8047 +send(8) nullUD g10<8,8,1>UD 0x080a8047 urb MsgDesc: 4 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x080a8057 +send(8) nullUD g11<8,8,1>UD 0x080a8057 urb MsgDesc: 5 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x080a8067 +send(8) nullUD g12<8,8,1>UD 0x080a8067 urb MsgDesc: 6 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x080a8077 +send(8) nullUD g13<8,8,1>UD 0x080a8077 urb MsgDesc: 7 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x080a8087 +send(8) nullUD g14<8,8,1>UD 0x080a8087 urb MsgDesc: 8 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x080a8097 +send(8) nullUD g15<8,8,1>UD 0x080a8097 urb MsgDesc: 9 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x080a80a7 +send(8) nullUD g16<8,8,1>UD 0x080a80a7 urb MsgDesc: 10 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x080a80b7 +send(8) nullUD g17<8,8,1>UD 0x080a80b7 urb MsgDesc: 11 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x080a80c7 +send(8) nullUD g18<8,8,1>UD 0x080a80c7 urb MsgDesc: 12 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a80d7 +send(8) nullUD g19<8,8,1>UD 0x080a80d7 urb MsgDesc: 13 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080a80e7 +send(8) nullUD g20<8,8,1>UD 0x080a80e7 urb MsgDesc: 14 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080a80f7 +send(8) nullUD g21<8,8,1>UD 0x080a80f7 urb MsgDesc: 15 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080a8107 +send(8) nullUD g22<8,8,1>UD 0x080a8107 urb MsgDesc: 16 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080a8117 +send(8) nullUD g23<8,8,1>UD 0x080a8117 urb MsgDesc: 17 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080a8127 +send(8) nullUD g24<8,8,1>UD 0x080a8127 urb MsgDesc: 18 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x080a8137 +send(8) nullUD g25<8,8,1>UD 0x080a8137 urb MsgDesc: 19 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x080a8147 +send(8) nullUD g26<8,8,1>UD 0x080a8147 urb MsgDesc: 20 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x080a8157 +send(8) nullUD g27<8,8,1>UD 0x080a8157 urb MsgDesc: 21 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x080a8167 +send(8) nullUD g28<8,8,1>UD 0x080a8167 urb MsgDesc: 22 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x080a8177 +send(8) nullUD g29<8,8,1>UD 0x080a8177 urb MsgDesc: 23 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x080a8187 +send(8) nullUD g30<8,8,1>UD 0x080a8187 urb MsgDesc: 24 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x080a8197 +send(8) nullUD g31<8,8,1>UD 0x080a8197 urb MsgDesc: 25 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x080a81a7 +send(8) nullUD g32<8,8,1>UD 0x080a81a7 urb MsgDesc: 26 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x080a81b7 +send(8) nullUD g33<8,8,1>UD 0x080a81b7 urb MsgDesc: 27 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x080a81c7 +send(8) nullUD g34<8,8,1>UD 0x080a81c7 urb MsgDesc: 28 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080a81d7 +send(8) nullUD g35<8,8,1>UD 0x080a81d7 urb MsgDesc: 29 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080a81e7 +send(8) nullUD g36<8,8,1>UD 0x080a81e7 urb MsgDesc: 30 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080a81f7 +send(8) nullUD g37<8,8,1>UD 0x080a81f7 urb MsgDesc: 31 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080a8207 +send(8) nullUD g38<8,8,1>UD 0x080a8207 urb MsgDesc: 32 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080a8217 +send(8) nullUD g39<8,8,1>UD 0x080a8217 urb MsgDesc: 33 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; send(8) g18<1>UW g19<8,8,1>UD 0x04115e00 hdc1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; @@ -2556,41 +2556,41 @@ send(8) g16<1>UD g75<8,8,1>UD 0x02480618 urb MsgDesc: 97 SIMD8 read mlen 1 rlen 4 { align1 1Q }; send(8) g20<1>UD g75<8,8,1>UD 0x02480818 urb MsgDesc: 129 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a00c7 +send(8) nullUD g20<8,8,1>UD 0x0c0a00c7 urb MsgDesc: 12 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a00d7 +send(8) nullUD g21<8,8,1>UD 0x0c0a00d7 urb MsgDesc: 13 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a00e7 +send(8) nullUD g22<8,8,1>UD 0x0c0a00e7 urb MsgDesc: 14 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a00f7 +send(8) nullUD g23<8,8,1>UD 0x0c0a00f7 urb MsgDesc: 15 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a0107 +send(8) nullUD g24<8,8,1>UD 0x0c0a0107 urb MsgDesc: 16 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a0117 +send(8) nullUD g25<8,8,1>UD 0x0c0a0117 urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a0137 +send(8) nullUD g27<8,8,1>UD 0x0c0a0137 urb MsgDesc: 19 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a0147 +send(8) nullUD g28<8,8,1>UD 0x0c0a0147 urb MsgDesc: 20 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a0157 +send(8) nullUD g29<8,8,1>UD 0x0c0a0157 urb MsgDesc: 21 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0167 +send(8) nullUD g30<8,8,1>UD 0x0c0a0167 urb MsgDesc: 22 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a0177 +send(8) nullUD g31<8,8,1>UD 0x0c0a0177 urb MsgDesc: 23 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a0187 +send(8) nullUD g32<8,8,1>UD 0x0c0a0187 urb MsgDesc: 24 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a01a7 +send(8) nullUD g34<8,8,1>UD 0x0c0a01a7 urb MsgDesc: 26 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a01b7 +send(8) nullUD g35<8,8,1>UD 0x0c0a01b7 urb MsgDesc: 27 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a01c7 +send(8) nullUD g36<8,8,1>UD 0x0c0a01c7 urb MsgDesc: 28 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a01d7 +send(8) nullUD g37<8,8,1>UD 0x0c0a01d7 urb MsgDesc: 29 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a01e7 +send(8) nullUD g38<8,8,1>UD 0x0c0a01e7 urb MsgDesc: 30 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a01f7 +send(8) nullUD g39<8,8,1>UD 0x0c0a01f7 urb MsgDesc: 31 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; send(16) g46<1>UD g12<0,1,0>UD 0x02280302 hdc:ro MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; @@ -2622,27 +2622,27 @@ send(8) g18<1>UW g58<8,8,1>UD 0x0242ab0b sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; send(8) g22<1>UW g59<8,8,1>UD 0x0242ac0c sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x0c088027 +send(8) nullUD g9<8,8,1>UD 0x0c088027 urb MsgDesc: 2 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x0c088047 +send(8) nullUD g10<8,8,1>UD 0x0c088047 urb MsgDesc: 4 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0c088067 +send(8) nullUD g11<8,8,1>UD 0x0c088067 urb MsgDesc: 6 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088037 +send(8) nullUD g6<8,8,1>UD 0x0c088037 urb MsgDesc: 3 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0c088057 +send(8) nullUD g7<8,8,1>UD 0x0c088057 urb MsgDesc: 5 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0c088077 +send(8) nullUD g8<8,8,1>UD 0x0c088077 urb MsgDesc: 7 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0197 +send(8) nullUD g6<8,8,1>F 0x140a0197 urb MsgDesc: 25 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01b7 +send(8) nullUD g6<8,8,1>F 0x140a01b7 urb MsgDesc: 27 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01d7 +send(8) nullUD g6<8,8,1>F 0x140a01d7 urb MsgDesc: 29 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01f7 +send(8) nullUD g6<8,8,1>F 0x140a01f7 urb MsgDesc: 31 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0217 +send(8) nullUD g120<8,8,1>F 0x8c0a0217 urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g8<1>UD g6<8,8,1>UD 0x041a0318 urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; @@ -2660,69 +2660,69 @@ send(8) g9<1>UD g11<8,8,1>UD 0x041a0618 urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; send(8) g10<1>UD g11<8,8,1>UD 0x041a0818 urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x080a8227 +send(8) nullUD g10<8,8,1>UD 0x080a8227 urb MsgDesc: 34 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x080a8237 +send(8) nullUD g11<8,8,1>UD 0x080a8237 urb MsgDesc: 35 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x080a8247 +send(8) nullUD g12<8,8,1>UD 0x080a8247 urb MsgDesc: 36 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x080a8257 +send(8) nullUD g13<8,8,1>UD 0x080a8257 urb MsgDesc: 37 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x080a8267 +send(8) nullUD g14<8,8,1>UD 0x080a8267 urb MsgDesc: 38 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x080a8277 +send(8) nullUD g15<8,8,1>UD 0x080a8277 urb MsgDesc: 39 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x080a8287 +send(8) nullUD g16<8,8,1>UD 0x080a8287 urb MsgDesc: 40 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x080a8297 +send(8) nullUD g17<8,8,1>UD 0x080a8297 urb MsgDesc: 41 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x080a82a7 +send(8) nullUD g18<8,8,1>UD 0x080a82a7 urb MsgDesc: 42 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a82b7 +send(8) nullUD g19<8,8,1>UD 0x080a82b7 urb MsgDesc: 43 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080a82c7 +send(8) nullUD g20<8,8,1>UD 0x080a82c7 urb MsgDesc: 44 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080a82d7 +send(8) nullUD g21<8,8,1>UD 0x080a82d7 urb MsgDesc: 45 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080a82e7 +send(8) nullUD g22<8,8,1>UD 0x080a82e7 urb MsgDesc: 46 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080a82f7 +send(8) nullUD g23<8,8,1>UD 0x080a82f7 urb MsgDesc: 47 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080a8307 +send(8) nullUD g24<8,8,1>UD 0x080a8307 urb MsgDesc: 48 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x080a8317 +send(8) nullUD g25<8,8,1>UD 0x080a8317 urb MsgDesc: 49 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x080a8327 +send(8) nullUD g26<8,8,1>UD 0x080a8327 urb MsgDesc: 50 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x080a8337 +send(8) nullUD g27<8,8,1>UD 0x080a8337 urb MsgDesc: 51 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x080a8347 +send(8) nullUD g28<8,8,1>UD 0x080a8347 urb MsgDesc: 52 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x080a8357 +send(8) nullUD g29<8,8,1>UD 0x080a8357 urb MsgDesc: 53 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x080a8367 +send(8) nullUD g30<8,8,1>UD 0x080a8367 urb MsgDesc: 54 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x080a8377 +send(8) nullUD g31<8,8,1>UD 0x080a8377 urb MsgDesc: 55 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x080a8387 +send(8) nullUD g32<8,8,1>UD 0x080a8387 urb MsgDesc: 56 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x080a8397 +send(8) nullUD g33<8,8,1>UD 0x080a8397 urb MsgDesc: 57 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x080a83a7 +send(8) nullUD g34<8,8,1>UD 0x080a83a7 urb MsgDesc: 58 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080a83b7 +send(8) nullUD g35<8,8,1>UD 0x080a83b7 urb MsgDesc: 59 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080a83c7 +send(8) nullUD g36<8,8,1>UD 0x080a83c7 urb MsgDesc: 60 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080a83d7 +send(8) nullUD g37<8,8,1>UD 0x080a83d7 urb MsgDesc: 61 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080a83e7 +send(8) nullUD g38<8,8,1>UD 0x080a83e7 urb MsgDesc: 62 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080a83f7 +send(8) nullUD g39<8,8,1>UD 0x080a83f7 urb MsgDesc: 63 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; send(8) g8<1>UD g9<8,8,1>UD 0x02480008 urb MsgDesc: 0 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080007 +send(8) nullUD g123<8,8,1>F 0x8a080007 urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g4<1>UW g2<8,8,1>UD 0x04215c01 hdc1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q }; @@ -2742,7 +2742,7 @@ send(16) g2<1>UW g11<8,8,1>UD 0x0c845001 sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; send(16) g10<1>UW g18<8,8,1>UD 0x0c845102 sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; -send(8) null<1>F g121<8,8,1>F 0x8a080197 +send(8) nullUD g121<8,8,1>F 0x8a080197 urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; send(8) g124<1>UW g6<8,8,1>UD 0x02415000 hdc1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; @@ -2974,7 +2974,7 @@ send(8) g11<1>UW g4<8,8,1>UD 0x04415002 hdc1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; send(8) g7<1>UW g5<8,8,1>UD 0x04416002 hdc1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; -send(8) null<1>F g16<8,8,1>UD 0x0e0a8057 +send(8) nullUD g16<8,8,1>UD 0x0e0a8057 urb MsgDesc: 5 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; send(8) g6<1>UD g18<8,8,1>UD 0x043a0318 urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; @@ -2992,65 +2992,65 @@ send(8) g17<1>UD g23<8,8,1>UD 0x043a0618 urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; send(8) g20<1>UD g23<8,8,1>UD 0x043a0818 urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a8227 +send(8) nullUD g12<8,8,1>UD 0x0c0a8227 urb MsgDesc: 34 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0c0a8237 +send(8) nullUD g13<8,8,1>UD 0x0c0a8237 urb MsgDesc: 35 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8247 +send(8) nullUD g14<8,8,1>UD 0x0c0a8247 urb MsgDesc: 36 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8257 +send(8) nullUD g15<8,8,1>UD 0x0c0a8257 urb MsgDesc: 37 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8267 +send(8) nullUD g16<8,8,1>UD 0x0c0a8267 urb MsgDesc: 38 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a8277 +send(8) nullUD g17<8,8,1>UD 0x0c0a8277 urb MsgDesc: 39 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a8287 +send(8) nullUD g18<8,8,1>UD 0x0c0a8287 urb MsgDesc: 40 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a8297 +send(8) nullUD g19<8,8,1>UD 0x0c0a8297 urb MsgDesc: 41 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a82a7 +send(8) nullUD g20<8,8,1>UD 0x0c0a82a7 urb MsgDesc: 42 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a82b7 +send(8) nullUD g21<8,8,1>UD 0x0c0a82b7 urb MsgDesc: 43 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a82c7 +send(8) nullUD g22<8,8,1>UD 0x0c0a82c7 urb MsgDesc: 44 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a82d7 +send(8) nullUD g23<8,8,1>UD 0x0c0a82d7 urb MsgDesc: 45 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a82e7 +send(8) nullUD g24<8,8,1>UD 0x0c0a82e7 urb MsgDesc: 46 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a82f7 +send(8) nullUD g25<8,8,1>UD 0x0c0a82f7 urb MsgDesc: 47 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a8307 +send(8) nullUD g26<8,8,1>UD 0x0c0a8307 urb MsgDesc: 48 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a8317 +send(8) nullUD g27<8,8,1>UD 0x0c0a8317 urb MsgDesc: 49 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a8327 +send(8) nullUD g28<8,8,1>UD 0x0c0a8327 urb MsgDesc: 50 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a8337 +send(8) nullUD g29<8,8,1>UD 0x0c0a8337 urb MsgDesc: 51 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a8347 +send(8) nullUD g30<8,8,1>UD 0x0c0a8347 urb MsgDesc: 52 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a8357 +send(8) nullUD g31<8,8,1>UD 0x0c0a8357 urb MsgDesc: 53 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a8367 +send(8) nullUD g32<8,8,1>UD 0x0c0a8367 urb MsgDesc: 54 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a8377 +send(8) nullUD g33<8,8,1>UD 0x0c0a8377 urb MsgDesc: 55 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a8387 +send(8) nullUD g34<8,8,1>UD 0x0c0a8387 urb MsgDesc: 56 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a8397 +send(8) nullUD g35<8,8,1>UD 0x0c0a8397 urb MsgDesc: 57 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a83a7 +send(8) nullUD g36<8,8,1>UD 0x0c0a83a7 urb MsgDesc: 58 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a83b7 +send(8) nullUD g37<8,8,1>UD 0x0c0a83b7 urb MsgDesc: 59 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a83c7 +send(8) nullUD g38<8,8,1>UD 0x0c0a83c7 urb MsgDesc: 60 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a83d7 +send(8) nullUD g39<8,8,1>UD 0x0c0a83d7 urb MsgDesc: 61 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a83e7 +send(8) nullUD g40<8,8,1>UD 0x0c0a83e7 urb MsgDesc: 62 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a83f7 +send(8) nullUD g41<8,8,1>UD 0x0c0a83f7 urb MsgDesc: 63 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; send(8) g8<1>UW g7<8,8,1>UD 0x10134001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q }; @@ -3132,11 +3132,11 @@ send(8) g2<1>UD g2<8,8,1>UD 0x043a01f8 urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; send(8) g2<1>UD g2<8,8,1>UD 0x043a0208 urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) null<1>F g11<8,8,1>F 0x140a0047 +send(8) nullUD g11<8,8,1>F 0x140a0047 urb MsgDesc: 4 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>F 0x140a0087 +send(8) nullUD g31<8,8,1>F 0x140a0087 urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0087 +send(8) nullUD g118<8,8,1>F 0x940a0087 urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; send(8) g14<1>UW g11<8,8,1>UD 0x0a4b0202 sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; @@ -3482,7 +3482,7 @@ send(8) g2<1>UW g2<8,8,1>UD 0x06323001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; send(16) g2<1>UW g24<8,8,1>UD 0x0c643001 sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0117 +send(8) nullUD g120<8,8,1>F 0x8c0a0117 urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; send(8) g11<1>UD g1<8,8,1>UD 0x02380128 urb MsgDesc: 18 SIMD8 read mlen 1 rlen 3 { align1 1Q }; diff --git a/src/intel/compiler/brw/tests/gen9/send.expected b/src/intel/compiler/brw/tests/gen9/send.expected index 1f8d58ee764..fefce6b0383 100644 --- a/src/intel/compiler/brw/tests/gen9/send.expected +++ b/src/intel/compiler/brw/tests/gen9/send.expected @@ -1,33 +1,33 @@ -31 00 60 06 e0 3a 00 20 60 0f 8d 06 17 00 08 8a -31 00 60 06 e0 3a 00 20 a0 01 8d 06 07 00 08 12 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 27 00 08 8a +31 00 60 06 00 3a 00 20 60 0f 8d 06 17 00 08 8a +31 00 60 06 00 3a 00 20 a0 01 8d 06 07 00 08 12 +31 00 60 06 00 3a 00 20 60 0f 8d 06 27 00 08 8a 31 00 80 09 0c 02 20 21 40 00 00 06 00 03 28 02 -31 00 60 06 e0 3a 00 20 e0 0e 8d 06 17 00 08 92 -31 00 80 07 44 12 00 20 e0 0f 8d 06 10 00 00 82 +31 00 60 06 00 3a 00 20 e0 0e 8d 06 17 00 08 92 +31 00 80 07 04 12 00 20 e0 0f 8d 06 10 00 00 82 31 00 60 02 48 02 80 2f a0 01 8d 06 01 a0 43 06 31 00 80 02 48 02 00 2f e0 02 8d 06 01 a0 85 0c 31 00 60 06 08 02 40 21 40 00 8d 06 28 00 48 02 -31 00 60 06 e0 3a 00 20 00 01 8d 06 17 00 0a 14 -31 00 60 06 e0 3a 00 20 c0 0e 8d 06 17 00 0a 94 +31 00 60 06 00 3a 00 20 00 01 8d 06 17 00 0a 14 +31 00 60 06 00 3a 00 20 c0 0e 8d 06 17 00 0a 94 31 00 60 02 48 02 40 20 40 01 8d 06 01 70 42 08 31 00 80 02 48 02 40 20 40 02 8d 06 01 70 84 10 -31 00 60 06 e0 02 00 20 60 01 8d 06 37 00 0a 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 27 00 08 0a -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0a -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 08 -31 00 60 06 e0 02 00 20 40 00 8d 06 17 80 08 06 -31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0a -31 00 60 06 e0 02 00 20 a0 0f 8d 06 07 80 08 86 +31 00 60 06 00 02 00 20 60 01 8d 06 37 00 0a 0c +31 00 60 06 00 02 00 20 c0 00 8d 06 27 00 08 0a +31 00 60 06 00 02 00 20 c0 00 8d 06 17 80 08 0c +31 00 60 06 00 02 00 20 c0 00 8d 06 17 80 08 0a +31 00 60 06 00 02 00 20 c0 00 8d 06 17 80 08 08 +31 00 60 06 00 02 00 20 40 00 8d 06 17 80 08 06 +31 00 60 06 00 02 00 20 c0 00 8d 06 07 80 08 0c +31 00 60 06 00 02 00 20 c0 00 8d 06 07 80 08 0a +31 00 60 06 00 02 00 20 a0 0f 8d 06 07 80 08 86 31 00 60 02 48 02 e0 20 e0 00 8d 06 00 a0 43 04 31 00 60 02 48 02 40 21 c0 00 8d 06 01 a0 22 02 31 00 60 02 48 02 40 20 60 02 8d 06 01 80 4a 08 31 00 80 02 48 02 20 23 00 02 8d 06 01 a0 44 04 31 00 80 02 48 02 c0 21 e0 00 8d 06 01 80 8c 0e -31 00 60 06 e0 3a 00 20 60 01 8d 06 17 00 08 12 -31 00 60 06 e0 3a 00 20 80 02 8d 06 37 00 08 12 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 57 00 08 8a +31 00 60 06 00 3a 00 20 60 01 8d 06 17 00 08 12 +31 00 60 06 00 3a 00 20 80 02 8d 06 37 00 08 12 +31 00 60 06 00 3a 00 20 60 0f 8d 06 57 00 08 8a 31 00 60 02 48 02 20 21 c0 00 8d 06 01 d0 13 06 31 00 80 02 48 02 80 21 c0 01 8d 06 01 d0 25 0c 31 00 60 02 48 02 40 20 c0 01 8d 06 01 d0 43 06 @@ -43,7 +43,7 @@ 31 00 60 02 48 02 60 21 20 01 8d 06 00 a0 22 02 31 00 60 02 48 02 80 2f a0 01 8d 06 00 80 4a 06 31 00 60 02 48 02 80 21 a0 00 8d 06 00 70 42 02 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 37 00 08 8a +31 00 60 06 00 3a 00 20 60 0f 8d 06 37 00 08 8a 31 00 60 02 48 02 c0 20 60 01 8d 06 01 40 4a 14 31 00 61 0c 4a 02 a0 2f 60 00 8d 06 01 b5 10 02 31 00 81 0c 4a 02 40 2f 80 00 8d 06 01 a5 20 04 @@ -56,21 +56,21 @@ 31 00 80 02 48 02 40 21 80 01 8d 06 01 60 2c 12 31 00 80 02 48 02 80 21 a0 02 8d 06 02 61 2c 12 31 00 60 02 48 02 80 2f 60 00 8d 06 00 e0 43 0a -31 00 60 06 e0 3a 00 20 e0 0e 8d 06 27 00 08 92 +31 00 60 06 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31 00 60 02 48 02 40 22 40 07 8d 06 0b ab 42 02 31 00 60 02 48 02 c0 22 60 07 8d 06 0c ac 42 02 -31 00 60 06 e0 02 00 20 20 01 8d 06 27 80 08 0c -31 00 60 06 e0 02 00 20 40 01 8d 06 47 80 08 0c -31 00 60 06 e0 02 00 20 60 01 8d 06 67 80 08 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 37 80 08 0c -31 00 60 06 e0 02 00 20 e0 00 8d 06 57 80 08 0c -31 00 60 06 e0 02 00 20 00 01 8d 06 77 80 08 0c -31 00 60 06 e0 3a 00 20 c0 00 8d 06 97 01 0a 14 -31 00 60 06 e0 3a 00 20 c0 00 8d 06 b7 01 0a 14 -31 00 60 06 e0 3a 00 20 c0 00 8d 06 d7 01 0a 14 -31 00 60 06 e0 3a 00 20 c0 00 8d 06 f7 01 0a 14 -31 00 60 06 e0 3a 00 20 00 0f 8d 06 17 02 0a 8c +31 00 60 06 00 02 00 20 20 01 8d 06 27 80 08 0c +31 00 60 06 00 02 00 20 40 01 8d 06 47 80 08 0c +31 00 60 06 00 02 00 20 60 01 8d 06 67 80 08 0c +31 00 60 06 00 02 00 20 c0 00 8d 06 37 80 08 0c +31 00 60 06 00 02 00 20 e0 00 8d 06 57 80 08 0c +31 00 60 06 00 02 00 20 00 01 8d 06 77 80 08 0c +31 00 60 06 00 3a 00 20 c0 00 8d 06 97 01 0a 14 +31 00 60 06 00 3a 00 20 c0 00 8d 06 b7 01 0a 14 +31 00 60 06 00 3a 00 20 c0 00 8d 06 d7 01 0a 14 +31 00 60 06 00 3a 00 20 c0 00 8d 06 f7 01 0a 14 +31 00 60 06 00 3a 00 20 00 0f 8d 06 17 02 0a 8c 31 00 60 06 08 02 00 21 c0 00 8d 06 18 03 1a 04 31 00 60 06 08 02 20 21 c0 00 8d 06 18 05 1a 04 31 00 60 06 08 02 40 21 c0 00 8d 06 18 07 1a 04 @@ -1329,38 +1329,38 @@ 31 00 60 06 08 02 00 21 60 01 8d 06 18 04 1a 04 31 00 60 06 08 02 20 21 60 01 8d 06 18 06 1a 04 31 00 60 06 08 02 40 21 60 01 8d 06 18 08 1a 04 -31 00 60 06 e0 02 00 20 40 01 8d 06 27 82 0a 08 -31 00 60 06 e0 02 00 20 60 01 8d 06 37 82 0a 08 -31 00 60 06 e0 02 00 20 80 01 8d 06 47 82 0a 08 -31 00 60 06 e0 02 00 20 a0 01 8d 06 57 82 0a 08 -31 00 60 06 e0 02 00 20 c0 01 8d 06 67 82 0a 08 -31 00 60 06 e0 02 00 20 e0 01 8d 06 77 82 0a 08 -31 00 60 06 e0 02 00 20 00 02 8d 06 87 82 0a 08 -31 00 60 06 e0 02 00 20 20 02 8d 06 97 82 0a 08 -31 00 60 06 e0 02 00 20 40 02 8d 06 a7 82 0a 08 -31 00 60 06 e0 02 00 20 60 02 8d 06 b7 82 0a 08 -31 00 60 06 e0 02 00 20 80 02 8d 06 c7 82 0a 08 -31 00 60 06 e0 02 00 20 a0 02 8d 06 d7 82 0a 08 -31 00 60 06 e0 02 00 20 c0 02 8d 06 e7 82 0a 08 -31 00 60 06 e0 02 00 20 e0 02 8d 06 f7 82 0a 08 -31 00 60 06 e0 02 00 20 00 03 8d 06 07 83 0a 08 -31 00 60 06 e0 02 00 20 20 03 8d 06 17 83 0a 08 -31 00 60 06 e0 02 00 20 40 03 8d 06 27 83 0a 08 -31 00 60 06 e0 02 00 20 60 03 8d 06 37 83 0a 08 -31 00 60 06 e0 02 00 20 80 03 8d 06 47 83 0a 08 -31 00 60 06 e0 02 00 20 a0 03 8d 06 57 83 0a 08 -31 00 60 06 e0 02 00 20 c0 03 8d 06 67 83 0a 08 -31 00 60 06 e0 02 00 20 e0 03 8d 06 77 83 0a 08 -31 00 60 06 e0 02 00 20 00 04 8d 06 87 83 0a 08 -31 00 60 06 e0 02 00 20 20 04 8d 06 97 83 0a 08 -31 00 60 06 e0 02 00 20 40 04 8d 06 a7 83 0a 08 -31 00 60 06 e0 02 00 20 60 04 8d 06 b7 83 0a 08 -31 00 60 06 e0 02 00 20 80 04 8d 06 c7 83 0a 08 -31 00 60 06 e0 02 00 20 a0 04 8d 06 d7 83 0a 08 -31 00 60 06 e0 02 00 20 c0 04 8d 06 e7 83 0a 08 -31 00 60 06 e0 02 00 20 e0 04 8d 06 f7 83 0a 08 +31 00 60 06 00 02 00 20 40 01 8d 06 27 82 0a 08 +31 00 60 06 00 02 00 20 60 01 8d 06 37 82 0a 08 +31 00 60 06 00 02 00 20 80 01 8d 06 47 82 0a 08 +31 00 60 06 00 02 00 20 a0 01 8d 06 57 82 0a 08 +31 00 60 06 00 02 00 20 c0 01 8d 06 67 82 0a 08 +31 00 60 06 00 02 00 20 e0 01 8d 06 77 82 0a 08 +31 00 60 06 00 02 00 20 00 02 8d 06 87 82 0a 08 +31 00 60 06 00 02 00 20 20 02 8d 06 97 82 0a 08 +31 00 60 06 00 02 00 20 40 02 8d 06 a7 82 0a 08 +31 00 60 06 00 02 00 20 60 02 8d 06 b7 82 0a 08 +31 00 60 06 00 02 00 20 80 02 8d 06 c7 82 0a 08 +31 00 60 06 00 02 00 20 a0 02 8d 06 d7 82 0a 08 +31 00 60 06 00 02 00 20 c0 02 8d 06 e7 82 0a 08 +31 00 60 06 00 02 00 20 e0 02 8d 06 f7 82 0a 08 +31 00 60 06 00 02 00 20 00 03 8d 06 07 83 0a 08 +31 00 60 06 00 02 00 20 20 03 8d 06 17 83 0a 08 +31 00 60 06 00 02 00 20 40 03 8d 06 27 83 0a 08 +31 00 60 06 00 02 00 20 60 03 8d 06 37 83 0a 08 +31 00 60 06 00 02 00 20 80 03 8d 06 47 83 0a 08 +31 00 60 06 00 02 00 20 a0 03 8d 06 57 83 0a 08 +31 00 60 06 00 02 00 20 c0 03 8d 06 67 83 0a 08 +31 00 60 06 00 02 00 20 e0 03 8d 06 77 83 0a 08 +31 00 60 06 00 02 00 20 00 04 8d 06 87 83 0a 08 +31 00 60 06 00 02 00 20 20 04 8d 06 97 83 0a 08 +31 00 60 06 00 02 00 20 40 04 8d 06 a7 83 0a 08 +31 00 60 06 00 02 00 20 60 04 8d 06 b7 83 0a 08 +31 00 60 06 00 02 00 20 80 04 8d 06 c7 83 0a 08 +31 00 60 06 00 02 00 20 a0 04 8d 06 d7 83 0a 08 +31 00 60 06 00 02 00 20 c0 04 8d 06 e7 83 0a 08 +31 00 60 06 00 02 00 20 e0 04 8d 06 f7 83 0a 08 31 00 60 06 08 02 00 21 20 01 8d 06 08 00 48 02 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 07 00 08 8a +31 00 60 06 00 3a 00 20 60 0f 8d 06 07 00 08 8a 31 00 60 0c 48 02 80 20 40 00 8d 06 01 5c 21 04 31 10 60 0c 48 02 00 25 c0 04 8d 06 01 6c 21 04 31 00 60 02 48 02 c0 20 60 01 8d 06 01 40 4a 10 @@ -1370,7 +1370,7 @@ 31 00 60 02 48 02 c0 20 40 01 8d 06 02 51 42 06 31 00 80 02 48 02 40 20 60 01 8d 06 01 50 84 0c 31 00 80 02 48 02 40 21 40 02 8d 06 02 51 84 0c -31 00 60 06 e0 3a 00 20 20 0f 8d 06 97 01 08 8a +31 00 60 06 00 3a 00 20 20 0f 8d 06 97 01 08 8a 31 00 60 0c 48 02 80 2f c0 00 8d 06 00 50 41 02 31 00 60 0c 48 02 80 2f c0 00 8d 06 00 50 41 06 31 00 60 0c 48 02 80 2f c0 00 8d 06 00 5c 21 02 @@ -1486,7 +1486,7 @@ 31 00 80 02 48 02 c0 20 40 00 8d 06 01 90 24 08 31 00 60 0c 48 02 60 21 80 00 8d 06 02 50 41 04 31 10 60 0c 48 02 e0 20 a0 00 8d 06 02 60 41 04 -31 00 60 06 e0 02 00 20 00 02 8d 06 57 80 0a 0e +31 00 60 06 00 02 00 20 00 02 8d 06 57 80 0a 0e 31 00 60 06 08 02 c0 20 40 02 8d 06 18 03 3a 04 31 00 60 06 08 02 20 21 40 02 8d 06 18 05 3a 04 31 00 60 06 08 02 80 21 40 02 8d 06 18 07 3a 04 @@ -1495,36 +1495,36 @@ 31 00 60 06 08 02 c0 21 e0 02 8d 06 18 04 3a 04 31 00 60 06 08 02 20 22 e0 02 8d 06 18 06 3a 04 31 00 60 06 08 02 80 22 e0 02 8d 06 18 08 3a 04 -31 00 60 06 e0 02 00 20 80 01 8d 06 27 82 0a 0c -31 00 60 06 e0 02 00 20 a0 01 8d 06 37 82 0a 0c -31 00 60 06 e0 02 00 20 c0 01 8d 06 47 82 0a 0c -31 00 60 06 e0 02 00 20 e0 01 8d 06 57 82 0a 0c -31 00 60 06 e0 02 00 20 00 02 8d 06 67 82 0a 0c -31 00 60 06 e0 02 00 20 20 02 8d 06 77 82 0a 0c -31 00 60 06 e0 02 00 20 40 02 8d 06 87 82 0a 0c -31 00 60 06 e0 02 00 20 60 02 8d 06 97 82 0a 0c -31 00 60 06 e0 02 00 20 80 02 8d 06 a7 82 0a 0c -31 00 60 06 e0 02 00 20 a0 02 8d 06 b7 82 0a 0c -31 00 60 06 e0 02 00 20 c0 02 8d 06 c7 82 0a 0c -31 00 60 06 e0 02 00 20 e0 02 8d 06 d7 82 0a 0c -31 00 60 06 e0 02 00 20 00 03 8d 06 e7 82 0a 0c -31 00 60 06 e0 02 00 20 20 03 8d 06 f7 82 0a 0c -31 00 60 06 e0 02 00 20 40 03 8d 06 07 83 0a 0c -31 00 60 06 e0 02 00 20 60 03 8d 06 17 83 0a 0c -31 00 60 06 e0 02 00 20 80 03 8d 06 27 83 0a 0c -31 00 60 06 e0 02 00 20 a0 03 8d 06 37 83 0a 0c -31 00 60 06 e0 02 00 20 c0 03 8d 06 47 83 0a 0c -31 00 60 06 e0 02 00 20 e0 03 8d 06 57 83 0a 0c -31 00 60 06 e0 02 00 20 00 04 8d 06 67 83 0a 0c -31 00 60 06 e0 02 00 20 20 04 8d 06 77 83 0a 0c -31 00 60 06 e0 02 00 20 40 04 8d 06 87 83 0a 0c -31 00 60 06 e0 02 00 20 60 04 8d 06 97 83 0a 0c -31 00 60 06 e0 02 00 20 80 04 8d 06 a7 83 0a 0c -31 00 60 06 e0 02 00 20 a0 04 8d 06 b7 83 0a 0c -31 00 60 06 e0 02 00 20 c0 04 8d 06 c7 83 0a 0c -31 00 60 06 e0 02 00 20 e0 04 8d 06 d7 83 0a 0c -31 00 60 06 e0 02 00 20 00 05 8d 06 e7 83 0a 0c -31 00 60 06 e0 02 00 20 20 05 8d 06 f7 83 0a 0c +31 00 60 06 00 02 00 20 80 01 8d 06 27 82 0a 0c +31 00 60 06 00 02 00 20 a0 01 8d 06 37 82 0a 0c +31 00 60 06 00 02 00 20 c0 01 8d 06 47 82 0a 0c +31 00 60 06 00 02 00 20 e0 01 8d 06 57 82 0a 0c +31 00 60 06 00 02 00 20 00 02 8d 06 67 82 0a 0c +31 00 60 06 00 02 00 20 20 02 8d 06 77 82 0a 0c +31 00 60 06 00 02 00 20 40 02 8d 06 87 82 0a 0c +31 00 60 06 00 02 00 20 60 02 8d 06 97 82 0a 0c +31 00 60 06 00 02 00 20 80 02 8d 06 a7 82 0a 0c +31 00 60 06 00 02 00 20 a0 02 8d 06 b7 82 0a 0c +31 00 60 06 00 02 00 20 c0 02 8d 06 c7 82 0a 0c +31 00 60 06 00 02 00 20 e0 02 8d 06 d7 82 0a 0c +31 00 60 06 00 02 00 20 00 03 8d 06 e7 82 0a 0c +31 00 60 06 00 02 00 20 20 03 8d 06 f7 82 0a 0c +31 00 60 06 00 02 00 20 40 03 8d 06 07 83 0a 0c +31 00 60 06 00 02 00 20 60 03 8d 06 17 83 0a 0c +31 00 60 06 00 02 00 20 80 03 8d 06 27 83 0a 0c +31 00 60 06 00 02 00 20 a0 03 8d 06 37 83 0a 0c +31 00 60 06 00 02 00 20 c0 03 8d 06 47 83 0a 0c +31 00 60 06 00 02 00 20 e0 03 8d 06 57 83 0a 0c +31 00 60 06 00 02 00 20 00 04 8d 06 67 83 0a 0c +31 00 60 06 00 02 00 20 20 04 8d 06 77 83 0a 0c +31 00 60 06 00 02 00 20 40 04 8d 06 87 83 0a 0c +31 00 60 06 00 02 00 20 60 04 8d 06 97 83 0a 0c +31 00 60 06 00 02 00 20 80 04 8d 06 a7 83 0a 0c +31 00 60 06 00 02 00 20 a0 04 8d 06 b7 83 0a 0c +31 00 60 06 00 02 00 20 c0 04 8d 06 c7 83 0a 0c +31 00 60 06 00 02 00 20 e0 04 8d 06 d7 83 0a 0c +31 00 60 06 00 02 00 20 00 05 8d 06 e7 83 0a 0c +31 00 60 06 00 02 00 20 20 05 8d 06 f7 83 0a 0c 31 00 60 02 48 02 00 21 e0 00 8d 06 01 40 13 10 31 00 60 02 48 02 20 21 e0 01 8d 06 02 41 13 10 31 00 60 06 08 02 00 22 00 02 8d 06 48 01 4a 04 @@ -1565,9 +1565,9 @@ 31 00 60 06 08 02 40 20 40 00 8d 06 e8 01 3a 04 31 00 60 06 08 02 40 20 40 00 8d 06 f8 01 3a 04 31 00 60 06 08 02 40 20 40 00 8d 06 08 02 3a 04 -31 00 60 06 e0 3a 00 20 60 01 8d 06 47 00 0a 14 -31 00 60 06 e0 3a 00 20 e0 03 8d 06 87 00 0a 14 -31 00 60 06 e0 3a 00 20 c0 0e 8d 06 87 00 0a 94 +31 00 60 06 00 3a 00 20 60 01 8d 06 47 00 0a 14 +31 00 60 06 00 3a 00 20 e0 03 8d 06 87 00 0a 14 +31 00 60 06 00 3a 00 20 c0 0e 8d 06 87 00 0a 94 31 00 60 02 48 02 c0 21 60 01 8d 06 02 02 4b 0a 31 00 60 02 48 02 40 22 40 02 8d 06 03 03 4b 0c 31 00 60 02 48 02 c0 22 00 03 8d 06 04 04 4b 08 @@ -1740,7 +1740,7 @@ 31 00 80 02 48 02 40 20 e0 00 8d 06 01 30 44 0c 31 00 60 02 48 02 40 20 40 00 8d 06 01 30 32 06 31 00 80 02 48 02 40 20 00 03 8d 06 01 30 64 0c -31 00 60 06 e0 3a 00 20 00 0f 8d 06 17 01 0a 8c +31 00 60 06 00 3a 00 20 00 0f 8d 06 17 01 0a 8c 31 00 60 06 08 02 60 21 20 00 8d 06 28 01 38 02 31 00 60 06 08 02 60 21 20 00 8d 06 38 01 38 02 31 00 60 06 08 02 60 21 20 00 8d 06 48 01 38 02 diff --git a/src/intel/compiler/brw/tests/gen9/sendc.asm b/src/intel/compiler/brw/tests/gen9/sendc.asm index 2d216dfacf6..72540d64871 100644 --- a/src/intel/compiler/brw/tests/gen9/sendc.asm +++ b/src/intel/compiler/brw/tests/gen9/sendc.asm @@ -1,98 +1,98 @@ -sendc(8) null<1>UW g124<0,1,0>F 0x88031400 +sendc(8) nullUD g124<0,1,0>F 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g120<0,1,0>F 0x90031000 +sendc(16) nullUD g120<0,1,0>F 0x90031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g114<0,1,0>F 0x82031100 +sendc(16) nullUD g114<0,1,0>F 0x82031100 render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880ba001 +sendc(8) nullUD g124<8,8,1>UD 0x880ba001 sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0da001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0da001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0001 +sendc(8) nullUD g125<8,8,1>UD 0x860a0001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c0001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -(+f0.1) sendc(8) null<1>UW g124<0,1,0>F 0x88031400 +(+f0.1) sendc(8) nullUD g124<0,1,0>F 0x88031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0be001 +sendc(8) nullUD g122<8,8,1>UD 0x8c0be001 sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960de001 +sendc(16) nullUD g117<8,8,1>UD 0x960de001 sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a0001 +sendc(8) nullUD g124<8,8,1>UD 0x880a0001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c0001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c0001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g118<8,8,1>UD 0x940a4001 +sendc(8) nullUD g118<8,8,1>UD 0x940a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD a0<0,1,0>UD 0x80000200 +sendc(8) nullUD g125<8,8,1>UD a0<0,1,0>UD 0x80000200 sampler MsgDesc: indirect { align1 1Q EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a4001 +sendc(8) nullUD g124<8,8,1>UD 0x880a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g121<8,8,1>UD 0x8e0bc001 +sendc(8) nullUD g121<8,8,1>UD 0x8e0bc001 sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g121<8,8,1>UD 0x8e0a4001 +sendc(8) nullUD g121<8,8,1>UD 0x8e0a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a2001 +sendc(8) nullUD g125<8,8,1>UD 0x860a2001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c2001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c2001 sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1401 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1401 render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1001 +sendc(16) nullUD g118<0,1,0>F 0x940b1001 render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g13<0,1,0>F 0x0e0b0401 +sendc(8) nullUD g13<0,1,0>F 0x0e0b0401 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1402 +sendc(8) nullUD g121<0,1,0>F 0x8e0b1402 render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g7<0,1,0>F 0x180b0001 +sendc(16) nullUD g7<0,1,0>F 0x180b0001 render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H }; -sendc(16) null<1>UW g116<0,1,0>F 0x980b1002 +sendc(16) nullUD g116<0,1,0>F 0x980b1002 render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a1001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a1001 sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c1001 +sendc(16) nullUD g119<8,8,1>UD 0x920c1001 sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; sendc(1) g2<1>UW g2<0,1,0>UW 0x0209c000 hdc0 MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0 { align1 WE_all 1N }; -sendc(8) null<1>UW g120<8,8,1>UD 0x900b4001 +sendc(8) nullUD g120<8,8,1>UD 0x900b4001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0b4001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0b4001 sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; sendc(8) g6<1>F g2<0,1,0>UD 0x044b4100 render MsgDesc: RT read MsgCtrl = 0x1 Surface = 0 mlen 2 rlen 4 { align1 1Q }; sendc(16) g9<1>F g27<0,1,0>UD 0x048b4000 render MsgDesc: RT read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 8 { align1 1H }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a3001 +sendc(8) nullUD g124<8,8,1>UD 0x880a3001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c3001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c3001 sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<0,1,0>F 0x8a031400 +sendc(8) nullUD g123<0,1,0>F 0x8a031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x94031000 +sendc(16) nullUD g118<0,1,0>F 0x94031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0400 +sendc(8) nullUD g5<0,1,0>F 0x0c0b0400 render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0401 +sendc(8) nullUD g5<0,1,0>F 0x0c0b0401 render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0402 +sendc(8) nullUD g5<0,1,0>F 0x0c0b0402 render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0403 +sendc(8) nullUD g5<0,1,0>F 0x0c0b0403 render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0404 +sendc(8) nullUD g5<0,1,0>F 0x0c0b0404 render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1405 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1405 render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0000 +sendc(16) nullUD g5<0,1,0>F 0x140b0000 render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0001 +sendc(16) nullUD g5<0,1,0>F 0x140b0001 render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0002 +sendc(16) nullUD g5<0,1,0>F 0x140b0002 render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0003 +sendc(16) nullUD g5<0,1,0>F 0x140b0003 render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0004 +sendc(16) nullUD g5<0,1,0>F 0x140b0004 render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1005 +sendc(16) nullUD g118<0,1,0>F 0x940b1005 render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT }; sendc(8) g6<1>F g6<0,1,0>UD 0x044b4101 render MsgDesc: RT read MsgCtrl = 0x1 Surface = 1 mlen 2 rlen 4 { align1 1Q }; @@ -100,7 +100,7 @@ sendc(8) g10<1>F g10<0,1,0>UD 0x044b4102 render MsgDesc: RT read MsgCtrl = 0x1 Surface = 2 mlen 2 rlen 4 { align1 1Q }; sendc(8) g14<1>F g14<0,1,0>UD 0x044b4103 render MsgDesc: RT read MsgCtrl = 0x1 Surface = 3 mlen 2 rlen 4 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1403 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1403 render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT }; sendc(16) g32<1>F g14<0,1,0>UD 0x048b4001 render MsgDesc: RT read MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 8 { align1 1H }; @@ -108,157 +108,157 @@ sendc(16) g40<1>F g16<0,1,0>UD 0x048b4002 render MsgDesc: RT read MsgCtrl = 0x0 Surface = 2 mlen 2 rlen 8 { align1 1H }; sendc(16) g48<1>F g18<0,1,0>UD 0x048b4003 render MsgDesc: RT read MsgCtrl = 0x0 Surface = 3 mlen 2 rlen 8 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1003 +sendc(16) nullUD g118<0,1,0>F 0x940b1003 render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a1001 +sendc(8) nullUD g124<8,8,1>UD 0x880a1001 sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c1001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c1001 sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860ba001 +sendc(8) nullUD g125<8,8,1>UD 0x860ba001 sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0da001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0da001 sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g126<8,8,1>UD 0x840a0001 +sendc(8) nullUD g126<8,8,1>UD 0x840a0001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g125<8,8,1>UD 0x860c0001 +sendc(16) nullUD g125<8,8,1>UD 0x860c0001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a2001 +sendc(8) nullUD g124<8,8,1>UD 0x880a2001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c2001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c2001 sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0be001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0be001 sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920de001 +sendc(16) nullUD g119<8,8,1>UD 0x920de001 sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g120<8,8,1>UD 0x900a4001 +sendc(8) nullUD g120<8,8,1>UD 0x900a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a2001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a2001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c2001 +sendc(16) nullUD g119<8,8,1>UD 0x920c2001 sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0304 +sendc(8) nullUD g125<8,8,1>UD 0x860a0304 sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0304 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c0304 sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a1001 +sendc(8) nullUD g122<8,8,1>UD 0x8c0a1001 sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960c1001 +sendc(16) nullUD g117<8,8,1>UD 0x960c1001 sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a3001 +sendc(8) nullUD g125<8,8,1>UD 0x860a3001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c3001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c3001 sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1402 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1402 render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1002 +sendc(16) nullUD g118<0,1,0>F 0x940b1002 render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a6001 +sendc(8) nullUD g124<8,8,1>UD 0x880a6001 sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c6001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c6001 sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a5001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a5001 sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c5001 +sendc(16) nullUD g119<8,8,1>UD 0x920c5001 sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a2001 +sendc(8) nullUD g122<8,8,1>UD 0x8c0a2001 sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960c2001 +sendc(16) nullUD g117<8,8,1>UD 0x960c2001 sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0bc001 +sendc(8) nullUD g122<8,8,1>UD 0x8c0bc001 sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960dc001 +sendc(16) nullUD g117<8,8,1>UD 0x960dc001 sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1400 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1000 +sendc(16) nullUD g118<0,1,0>F 0x940b1000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a7001 +sendc(8) nullUD g124<8,8,1>UD 0x880a7001 sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c7001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c7001 sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g118<0,1,0>F 0x940b1200 +sendc(8) nullUD g118<0,1,0>F 0x940b1200 render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g3<0,1,0>F 0x140b1200 +sendc(8) nullUD g3<0,1,0>F 0x140b1200 render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g118<0,1,0>F 0x940b1300 +sendc(8) nullUD g118<0,1,0>F 0x940b1300 render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a0001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a0001 sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c0001 +sendc(16) nullUD g119<8,8,1>UD 0x920c0001 sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; sendc(16) g11<1>F g37<0,1,0>UD 0x048b6000 render MsgDesc: RT read MsgCtrl = 0x32 Surface = 0 mlen 2 rlen 8 { align1 1H }; -sendc(8) null<1>UW g23<0,1,0>F 0x0c0b0405 +sendc(8) nullUD g23<0,1,0>F 0x0c0b0405 render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g29<0,1,0>F 0x0c0b0406 +sendc(8) nullUD g29<0,1,0>F 0x0c0b0406 render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1407 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1407 render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g57<0,1,0>F 0x140b0005 +sendc(16) nullUD g57<0,1,0>F 0x140b0005 render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g67<0,1,0>F 0x140b0006 +sendc(16) nullUD g67<0,1,0>F 0x140b0006 render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1007 +sendc(16) nullUD g118<0,1,0>F 0x940b1007 render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a1001 +sendc(8) nullUD g125<8,8,1>UD 0x860a1001 sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c1001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c1001 sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g10<0,1,0>F 0x0e0b0400 +sendc(8) nullUD g10<0,1,0>F 0x0e0b0400 render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1401 +sendc(8) nullUD g121<0,1,0>F 0x8e0b1401 render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g2<0,1,0>F 0x160b0000 +sendc(16) nullUD g2<0,1,0>F 0x160b0000 render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H }; -sendc(16) null<1>UW g117<0,1,0>F 0x960b1001 +sendc(16) nullUD g117<0,1,0>F 0x960b1001 render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1404 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1404 render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1004 +sendc(16) nullUD g118<0,1,0>F 0x940b1004 render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1406 +sendc(8) nullUD g122<0,1,0>F 0x8c0b1406 render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1006 +sendc(16) nullUD g118<0,1,0>F 0x940b1006 render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g119<0,1,0>F 0x92031000 +sendc(16) nullUD g119<0,1,0>F 0x92031000 render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g116<0,1,0>F 0x980b1001 +sendc(16) nullUD g116<0,1,0>F 0x980b1001 render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a6001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a6001 sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c6001 +sendc(16) nullUD g119<8,8,1>UD 0x920c6001 sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0102 +sendc(8) nullUD g125<8,8,1>UD 0x860a0102 sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0102 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c0102 sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a5001 +sendc(8) nullUD g124<8,8,1>UD 0x880a5001 sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c5001 +sendc(16) nullUD g121<8,8,1>UD 0x8e0c5001 sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a4001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a4001 sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a3001 +sendc(8) nullUD g123<8,8,1>UD 0x8a0a3001 sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c3001 +sendc(16) nullUD g119<8,8,1>UD 0x920c3001 sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0f10 +sendc(8) nullUD g125<8,8,1>UD 0x860a0f10 sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0f10 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c0f10 sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g126<8,8,1>UD 0x840a0102 +sendc(8) nullUD g126<8,8,1>UD 0x840a0102 sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g125<8,8,1>UD 0x860c0102 +sendc(16) nullUD g125<8,8,1>UD 0x860c0102 sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g11<0,1,0>F 0x180b0000 +sendc(16) nullUD g11<0,1,0>F 0x180b0000 render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c031400 +sendc(8) nullUD g122<0,1,0>F 0x8c031400 render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0506 +sendc(8) nullUD g125<8,8,1>UD 0x860a0506 sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0506 +sendc(16) nullUD g123<8,8,1>UD 0x8a0c0506 sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860b8001 +sendc(8) nullUD g125<8,8,1>UD 0x860b8001 sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0d8001 +sendc(16) nullUD g123<8,8,1>UD 0x8a0d8001 sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; diff --git a/src/intel/compiler/brw/tests/gen9/sendc.expected b/src/intel/compiler/brw/tests/gen9/sendc.expected index 9ddc39acd07..61a8a89c7bc 100644 --- a/src/intel/compiler/brw/tests/gen9/sendc.expected +++ b/src/intel/compiler/brw/tests/gen9/sendc.expected @@ -1,132 +1,132 @@ -32 00 60 05 40 3a 00 20 80 0f 00 06 00 14 03 88 -32 00 80 05 40 3a 00 20 00 0f 00 06 00 10 03 90 -32 00 80 05 40 3a 00 20 40 0e 00 06 00 11 03 82 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 a0 0b 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 a0 0d 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 00 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 00 0c 8a -32 00 61 05 41 3a 00 20 80 0f 00 06 00 14 03 88 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 e0 0b 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 e0 0d 96 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 00 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 00 0c 8e -32 00 60 02 40 02 00 20 c0 0e 8d 06 01 40 0a 94 -32 00 60 02 40 02 00 20 a0 2f 8d 00 00 02 00 80 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 40 0a 88 -32 00 60 02 40 02 00 20 20 0f 8d 06 01 c0 0b 8e -32 00 60 02 40 02 00 20 20 0f 8d 06 01 40 0a 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 20 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 20 0c 8a -32 00 60 05 40 3a 00 20 40 0f 00 06 01 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 01 10 0b 94 -32 00 60 05 40 3a 00 20 a0 01 00 06 01 04 0b 0e -32 00 60 05 40 3a 00 20 20 0f 00 06 02 14 0b 8e -32 00 80 05 40 3a 00 20 e0 00 00 06 01 00 0b 18 -32 00 80 05 40 3a 00 20 80 0e 00 06 02 10 0b 98 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 10 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 10 0c 92 +32 00 60 05 00 3a 00 20 80 0f 00 06 00 14 03 88 +32 00 80 05 00 3a 00 20 00 0f 00 06 00 10 03 90 +32 00 80 05 00 3a 00 20 40 0e 00 06 00 11 03 82 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 a0 0b 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 a0 0d 8e +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 00 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 00 0c 8a +32 00 61 05 01 3a 00 20 80 0f 00 06 00 14 03 88 +32 00 60 02 00 02 00 20 40 0f 8d 06 01 e0 0b 8c +32 00 80 02 00 02 00 20 a0 0e 8d 06 01 e0 0d 96 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 00 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 00 0c 8e +32 00 60 02 00 02 00 20 c0 0e 8d 06 01 40 0a 94 +32 00 60 02 00 02 00 20 a0 2f 8d 00 00 02 00 80 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 40 0a 88 +32 00 60 02 00 02 00 20 20 0f 8d 06 01 c0 0b 8e +32 00 60 02 00 02 00 20 20 0f 8d 06 01 40 0a 8e +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 20 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 20 0c 8a +32 00 60 05 00 3a 00 20 40 0f 00 06 01 14 0b 8c +32 00 80 05 00 3a 00 20 c0 0e 00 06 01 10 0b 94 +32 00 60 05 00 3a 00 20 a0 01 00 06 01 04 0b 0e +32 00 60 05 00 3a 00 20 20 0f 00 06 02 14 0b 8e +32 00 80 05 00 3a 00 20 e0 00 00 06 01 00 0b 18 +32 00 80 05 00 3a 00 20 80 0e 00 06 02 10 0b 98 +32 00 60 02 00 02 00 20 60 0f 8d 06 01 10 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 10 0c 92 32 00 00 0a 4c 12 40 20 40 00 00 06 00 c0 09 02 -32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0b 90 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0b 8a +32 00 60 02 00 02 00 20 00 0f 8d 06 01 40 0b 90 +32 00 60 02 00 02 00 20 60 0f 8d 06 01 40 0b 8a 32 00 60 05 e8 02 c0 20 40 00 00 06 00 41 4b 04 32 00 80 05 e8 02 20 21 60 03 00 06 00 40 8b 04 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 30 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 30 0c 8e -32 00 60 05 40 3a 00 20 60 0f 00 06 00 14 03 8a -32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 03 94 -32 00 60 05 40 3a 00 20 a0 00 00 06 00 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 01 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 02 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 03 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 04 04 0b 0c -32 00 60 05 40 3a 00 20 40 0f 00 06 05 14 0b 8c -32 00 80 05 40 3a 00 20 a0 00 00 06 00 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 01 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 02 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 03 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 04 00 0b 14 -32 00 80 05 40 3a 00 20 c0 0e 00 06 05 10 0b 94 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 30 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 30 0c 8e +32 00 60 05 00 3a 00 20 60 0f 00 06 00 14 03 8a +32 00 80 05 00 3a 00 20 c0 0e 00 06 00 10 03 94 +32 00 60 05 00 3a 00 20 a0 00 00 06 00 04 0b 0c +32 00 60 05 00 3a 00 20 a0 00 00 06 01 04 0b 0c +32 00 60 05 00 3a 00 20 a0 00 00 06 02 04 0b 0c +32 00 60 05 00 3a 00 20 a0 00 00 06 03 04 0b 0c +32 00 60 05 00 3a 00 20 a0 00 00 06 04 04 0b 0c +32 00 60 05 00 3a 00 20 40 0f 00 06 05 14 0b 8c +32 00 80 05 00 3a 00 20 a0 00 00 06 00 00 0b 14 +32 00 80 05 00 3a 00 20 a0 00 00 06 01 00 0b 14 +32 00 80 05 00 3a 00 20 a0 00 00 06 02 00 0b 14 +32 00 80 05 00 3a 00 20 a0 00 00 06 03 00 0b 14 +32 00 80 05 00 3a 00 20 a0 00 00 06 04 00 0b 14 +32 00 80 05 00 3a 00 20 c0 0e 00 06 05 10 0b 94 32 00 60 05 e8 02 c0 20 c0 00 00 06 01 41 4b 04 32 00 60 05 e8 02 40 21 40 01 00 06 02 41 4b 04 32 00 60 05 e8 02 c0 21 c0 01 00 06 03 41 4b 04 -32 00 60 05 40 3a 00 20 40 0f 00 06 03 14 0b 8c +32 00 60 05 00 3a 00 20 40 0f 00 06 03 14 0b 8c 32 00 80 05 e8 02 00 24 c0 01 00 06 01 40 8b 04 32 00 80 05 e8 02 00 25 00 02 00 06 02 40 8b 04 32 00 80 05 e8 02 00 26 40 02 00 06 03 40 8b 04 -32 00 80 05 40 3a 00 20 c0 0e 00 06 03 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 10 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 10 0c 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 a0 0b 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 a0 0d 8a -32 00 60 02 40 02 00 20 c0 0f 8d 06 01 00 0a 84 -32 00 80 02 40 02 00 20 a0 0f 8d 06 01 00 0c 86 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 20 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 20 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 e0 0b 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 e0 0d 92 -32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0a 90 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 20 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 20 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 04 03 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 04 03 0c 8a -32 00 60 02 40 02 00 20 40 0f 8d 06 01 10 0a 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 10 0c 96 -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 30 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 30 0c 8a -32 00 60 05 40 3a 00 20 40 0f 00 06 02 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 02 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 60 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 60 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 50 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 50 0c 92 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 20 0a 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 20 0c 96 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 c0 0b 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 c0 0d 96 -32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 70 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 70 0c 8e -32 00 60 05 40 3a 00 20 c0 0e 00 06 00 12 0b 94 -32 00 60 05 40 3a 00 20 60 00 00 06 00 12 0b 14 -32 10 60 05 40 3a 00 20 c0 0e 00 06 00 13 0b 94 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 00 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 00 0c 92 +32 00 80 05 00 3a 00 20 c0 0e 00 06 03 10 0b 94 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 10 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 10 0c 8e +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 a0 0b 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 a0 0d 8a +32 00 60 02 00 02 00 20 c0 0f 8d 06 01 00 0a 84 +32 00 80 02 00 02 00 20 a0 0f 8d 06 01 00 0c 86 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 20 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 20 0c 8e +32 00 60 02 00 02 00 20 60 0f 8d 06 01 e0 0b 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 e0 0d 92 +32 00 60 02 00 02 00 20 00 0f 8d 06 01 40 0a 90 +32 00 60 02 00 02 00 20 60 0f 8d 06 01 20 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 20 0c 92 +32 00 60 02 00 02 00 20 a0 0f 8d 06 04 03 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 04 03 0c 8a +32 00 60 02 00 02 00 20 40 0f 8d 06 01 10 0a 8c +32 00 80 02 00 02 00 20 a0 0e 8d 06 01 10 0c 96 +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 30 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 30 0c 8a +32 00 60 05 00 3a 00 20 40 0f 00 06 02 14 0b 8c +32 00 80 05 00 3a 00 20 c0 0e 00 06 02 10 0b 94 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 60 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 60 0c 8e +32 00 60 02 00 02 00 20 60 0f 8d 06 01 50 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 50 0c 92 +32 00 60 02 00 02 00 20 40 0f 8d 06 01 20 0a 8c +32 00 80 02 00 02 00 20 a0 0e 8d 06 01 20 0c 96 +32 00 60 02 00 02 00 20 40 0f 8d 06 01 c0 0b 8c +32 00 80 02 00 02 00 20 a0 0e 8d 06 01 c0 0d 96 +32 00 60 05 00 3a 00 20 40 0f 00 06 00 14 0b 8c +32 00 80 05 00 3a 00 20 c0 0e 00 06 00 10 0b 94 +32 00 60 02 00 02 00 20 80 0f 8d 06 01 70 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 70 0c 8e +32 00 60 05 00 3a 00 20 c0 0e 00 06 00 12 0b 94 +32 00 60 05 00 3a 00 20 60 00 00 06 00 12 0b 14 +32 10 60 05 00 3a 00 20 c0 0e 00 06 00 13 0b 94 +32 00 60 02 00 02 00 20 60 0f 8d 06 01 00 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 00 0c 92 32 00 80 05 e8 02 60 21 a0 04 00 06 00 60 8b 04 -32 00 60 05 40 3a 00 20 e0 02 00 06 05 04 0b 0c -32 00 60 05 40 3a 00 20 a0 03 00 06 06 04 0b 0c -32 00 60 05 40 3a 00 20 40 0f 00 06 07 14 0b 8c -32 00 80 05 40 3a 00 20 20 07 00 06 05 00 0b 14 -32 00 80 05 40 3a 00 20 60 08 00 06 06 00 0b 14 -32 00 80 05 40 3a 00 20 c0 0e 00 06 07 10 0b 94 -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 10 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 10 0c 8a -32 00 60 05 40 3a 00 20 40 01 00 06 00 04 0b 0e -32 00 60 05 40 3a 00 20 20 0f 00 06 01 14 0b 8e -32 00 80 05 40 3a 00 20 40 00 00 06 00 00 0b 16 -32 00 80 05 40 3a 00 20 a0 0e 00 06 01 10 0b 96 -32 00 60 05 40 3a 00 20 40 0f 00 06 04 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 04 10 0b 94 -32 00 60 05 40 3a 00 20 40 0f 00 06 06 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 06 10 0b 94 -32 00 80 05 40 3a 00 20 e0 0e 00 06 00 10 03 92 -32 00 80 05 40 3a 00 20 80 0e 00 06 01 10 0b 98 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 60 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 60 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 02 01 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 02 01 0c 8a -32 00 60 02 40 02 00 20 80 0f 8d 06 01 50 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 50 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0a 8a -32 00 60 02 40 02 00 20 60 0f 8d 06 01 30 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 30 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 10 0f 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 10 0f 0c 8a -32 00 60 02 40 02 00 20 c0 0f 8d 06 02 01 0a 84 -32 00 80 02 40 02 00 20 a0 0f 8d 06 02 01 0c 86 -32 00 80 05 40 3a 00 20 60 01 00 06 00 00 0b 18 -32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 03 8c -32 00 60 02 40 02 00 20 a0 0f 8d 06 06 05 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 06 05 0c 8a -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 80 0b 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 80 0d 8a +32 00 60 05 00 3a 00 20 e0 02 00 06 05 04 0b 0c +32 00 60 05 00 3a 00 20 a0 03 00 06 06 04 0b 0c +32 00 60 05 00 3a 00 20 40 0f 00 06 07 14 0b 8c +32 00 80 05 00 3a 00 20 20 07 00 06 05 00 0b 14 +32 00 80 05 00 3a 00 20 60 08 00 06 06 00 0b 14 +32 00 80 05 00 3a 00 20 c0 0e 00 06 07 10 0b 94 +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 10 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 10 0c 8a +32 00 60 05 00 3a 00 20 40 01 00 06 00 04 0b 0e +32 00 60 05 00 3a 00 20 20 0f 00 06 01 14 0b 8e +32 00 80 05 00 3a 00 20 40 00 00 06 00 00 0b 16 +32 00 80 05 00 3a 00 20 a0 0e 00 06 01 10 0b 96 +32 00 60 05 00 3a 00 20 40 0f 00 06 04 14 0b 8c +32 00 80 05 00 3a 00 20 c0 0e 00 06 04 10 0b 94 +32 00 60 05 00 3a 00 20 40 0f 00 06 06 14 0b 8c +32 00 80 05 00 3a 00 20 c0 0e 00 06 06 10 0b 94 +32 00 80 05 00 3a 00 20 e0 0e 00 06 00 10 03 92 +32 00 80 05 00 3a 00 20 80 0e 00 06 01 10 0b 98 +32 00 60 02 00 02 00 20 60 0f 8d 06 01 60 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 60 0c 92 +32 00 60 02 00 02 00 20 a0 0f 8d 06 02 01 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 02 01 0c 8a +32 00 60 02 00 02 00 20 80 0f 8d 06 01 50 0a 88 +32 00 80 02 00 02 00 20 20 0f 8d 06 01 50 0c 8e +32 00 60 02 00 02 00 20 60 0f 8d 06 01 40 0a 8a +32 00 60 02 00 02 00 20 60 0f 8d 06 01 30 0a 8a +32 00 80 02 00 02 00 20 e0 0e 8d 06 01 30 0c 92 +32 00 60 02 00 02 00 20 a0 0f 8d 06 10 0f 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 10 0f 0c 8a +32 00 60 02 00 02 00 20 c0 0f 8d 06 02 01 0a 84 +32 00 80 02 00 02 00 20 a0 0f 8d 06 02 01 0c 86 +32 00 80 05 00 3a 00 20 60 01 00 06 00 00 0b 18 +32 00 60 05 00 3a 00 20 40 0f 00 06 00 14 03 8c +32 00 60 02 00 02 00 20 a0 0f 8d 06 06 05 0a 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 06 05 0c 8a +32 00 60 02 00 02 00 20 a0 0f 8d 06 01 80 0b 86 +32 00 80 02 00 02 00 20 60 0f 8d 06 01 80 0d 8a diff --git a/src/intel/compiler/brw/tests/gen9/shr.asm b/src/intel/compiler/brw/tests/gen9/shr.asm index f64c61767d2..eff45f6e297 100644 --- a/src/intel/compiler/brw/tests/gen9/shr.asm +++ b/src/intel/compiler/brw/tests/gen9/shr.asm @@ -2,7 +2,7 @@ shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q }; shr(16) g43<1>UD g41<8,8,1>UD 0x00000001UD { align1 1H }; shr.z.f0.0(8) g3<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; shr(16) g8<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; -shr.z.f0.0(8) null<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; +shr.z.f0.0(8) nullUD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; shr(8) g3<1>UW g1.28<1,8,0>UB 0x76543210V { align1 1Q }; shr(8) g3<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q }; shr(16) g20<2>UW g15<8,8,1>UD g13<8,8,1>UW { align1 1H };