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r600g: implement output modifiers and use them to further optimize LRP
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4 changed files with 32 additions and 0 deletions
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@ -707,6 +707,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
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S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
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S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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@ -62,6 +62,7 @@ struct r600_bc_alu {
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unsigned bank_swizzle_force;
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unsigned bank_swizzle_force;
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u32 value[4];
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u32 value[4];
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int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
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int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
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unsigned omod;
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};
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};
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struct r600_bc_tex {
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struct r600_bc_tex {
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@ -1975,6 +1975,35 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
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r = tgsi_split_literal_constant(ctx, r600_src);
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r = tgsi_split_literal_constant(ctx, r600_src);
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if (r)
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if (r)
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return r;
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return r;
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/* optimize if it's just an equal balance */
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if(r600_src[0].sel == V_SQ_ALU_SRC_0_5) {
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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continue;
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memset(&alu, 0, sizeof(struct r600_bc_alu));
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alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
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alu.src[0] = r600_src[1];
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alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
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alu.src[1] = r600_src[2];
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alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
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alu.omod = 3;
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r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
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if (r)
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return r;
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alu.dst.chan = i;
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if (i == lasti) {
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alu.last = 1;
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}
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r = r600_bc_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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return 0;
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}
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/* 1 - src0 */
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/* 1 - src0 */
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for (i = 0; i < lasti + 1; i++) {
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for (i = 0; i < lasti + 1; i++) {
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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@ -61,6 +61,7 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
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S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
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S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
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S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
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