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radv: configure PA_CL_VRS_CNTL entirely from the cmd buffer

Browse source 
We already have all the information needed to configure it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22942>
This commit is contained in:
Samuel Pitoiset 2023-05-10 11:34:19 +02:00 • committed by Marge Bot
parent be0ba9a1c0
commit 088e25216f
3 changed files with 29 additions and 42 deletions
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40
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1896,8 +1896,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP |
RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP_ENABLE;
if (cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable ||
cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
if (cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
cmd_buffer->state.emitted_graphics_pipeline->uses_out_of_order_rast != pipeline->uses_out_of_order_rast ||
cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment ||
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
@ -1905,13 +1904,15 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable) {
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (device->physical_device->rad_info.gfx_level >= GFX10_3)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
}
if (cmd_buffer->state.emitted_graphics_pipeline->db_shader_control !=
pipeline->db_shader_control)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE;
if (cmd_buffer->state.emitted_graphics_pipeline->vrs.pa_cl_vrs_cntl !=
pipeline->vrs.pa_cl_vrs_cntl)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
}
radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
@ -2303,13 +2304,13 @@ radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
uint32_t rate_x = MIN2(2, d->vk.fsr.fragment_size.width) - 1;
uint32_t rate_y = MIN2(2, d->vk.fsr.fragment_size.height) - 1;
uint32_t pa_cl_vrs_cntl = pipeline->vrs.pa_cl_vrs_cntl;
uint32_t pipeline_comb_mode = d->vk.fsr.combiner_ops[0];
uint32_t htile_comb_mode = d->vk.fsr.combiner_ops[1];
uint32_t pa_cl_vrs_cntl = 0;
assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3);
@ -2345,6 +2346,16 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)
radeon_set_uconfig_reg(cmd_buffer->cs, R_03098C_GE_VRS_RATE,
S_03098C_RATE_X(rate_x) | S_03098C_RATE_Y(rate_y));
/* Disable VRS and use the rates from PS_ITER_SAMPLES if:
*
* 1) sample shading is enabled or per-sample interpolation is used by the fragment shader
* 2) the fragment shader reads gl_SampleMaskIn because the 16-bit sample coverage mask isn't
* enough for MSAA8x and 2x2 coarse shading isn't enough.
*/
if (cmd_buffer->state.ms.sample_shading_enable || ps->info.ps.reads_sample_mask_in) {
pa_cl_vrs_cntl |= S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE);
}
/* VERTEX_RATE_COMBINER_MODE controls the combiner mode between the
* draw rate and the vertex rate.
*/
@ -6612,11 +6623,18 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (gfx_level >= GFX10_3 &&
previous_ps && previous_ps->info.ps.reads_sample_mask_in != ps->info.ps.reads_sample_mask_in)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES |
RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
if (cmd_buffer->state.ms.sample_shading_enable != ps->info.ps.uses_sample_shading) {
cmd_buffer->state.ms.sample_shading_enable = ps->info.ps.uses_sample_shading;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.ms.sample_shading_enable != ps->info.ps.uses_sample_shading ||
cmd_buffer->state.ms.min_sample_shading != min_sample_shading) {
cmd_buffer->state.ms.sample_shading_enable = ps->info.ps.uses_sample_shading;
if (gfx_level >= GFX10_3)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
}
if (cmd_buffer->state.ms.min_sample_shading != min_sample_shading) {
cmd_buffer->state.ms.min_sample_shading = min_sample_shading;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
}

26
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -374,29 +374,6 @@ radv_pipeline_init_multisample_state(const struct radv_device *device,
ms->uses_user_sample_locations = state->ms && state->ms->sample_locations_enable;
}
static void
gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state)
{
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
struct radv_vrs_state *vrs = &pipeline->vrs;
if ((state->ms && state->ms->sample_shading_enable) || ps->info.ps.uses_sample_shading ||
ps->info.ps.reads_sample_mask_in) {
/* Disable VRS and use the rates from PS_ITER_SAMPLES if:
*
* 1) sample shading is enabled or per-sample interpolation is
* used by the fragment shader
* 2) the fragment shader reads gl_SampleMaskIn because the
* 16-bit sample coverage mask isn't enough for MSAA8x and
* 2x2 coarse shading isn't enough.
*/
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE);
} else {
vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_PASSTHRU);
}
}
static uint32_t
si_conv_tess_prim_to_gs_out(enum tess_primitive_mode prim)
{
@ -4061,9 +4038,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
radv_pipeline_init_input_assembly_state(device, pipeline);
radv_pipeline_init_dynamic_state(pipeline, &state, pCreateInfo);
if (device->physical_device->rad_info.gfx_level >= GFX10_3)
gfx103_pipeline_init_vrs_state(pipeline, &state);
struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, &state);
/* Copy the non-compacted SPI_SHADER_COL_FORMAT which is used to emit RBPLUS state. */

5
src/amd/vulkan/radv_private.h
View file

@ -2159,10 +2159,6 @@ enum {
extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);
struct radv_vrs_state {
uint32_t pa_cl_vrs_cntl;
};
struct radv_prim_vertex_count {
uint8_t min;
uint8_t incr;
@ -2260,7 +2256,6 @@ struct radv_graphics_pipeline {
struct radv_vs_input_state vs_input_state;
struct radv_multisample_state ms;
struct radv_vrs_state vrs;
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
uint32_t binding_stride[MAX_VBS];
uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];