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nvk: Use nv_device_info for class checks

Browse source 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
This commit is contained in:
Faith Ekstrand 2023-07-20 12:41:36 -05:00 • committed by Marge Bot
parent 1756e4601a
commit 088692d954
11 changed files with 50 additions and 46 deletions
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2
src/nouveau/vulkan/nvk_cmd_buffer.c
View file

@ -603,7 +603,7 @@ nvk_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
uint64_t offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0;
uint64_t cb_addr = nvk_buffer_address(buffer, offset);
if (nvk_cmd_buffer_device(cmd)->ctx->eng3d.cls >= TURING_A) {
if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A) {
struct nv_push *p = nvk_cmd_buffer_push(cmd, 6);
P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD));

4
src/nouveau/vulkan/nvk_cmd_copy.c
View file

@ -239,7 +239,7 @@ nouveau_copy_rect(struct nvk_cmd_buffer *cmd, struct nouveau_copy *copy)
else
P_NV90B5_SET_SRC_LAYER(p, 0);
if (nvk_cmd_buffer_device(cmd)->ctx->copy.cls >= 0xc1b5) {
if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_copy >= 0xc1b5) {
P_MTHD(p, NVC1B5, SRC_ORIGIN_X);
P_NVC1B5_SRC_ORIGIN_X(p, copy->src.offset_el.x * src_bw);
P_NVC1B5_SRC_ORIGIN_Y(p, copy->src.offset_el.y);
@ -275,7 +275,7 @@ nouveau_copy_rect(struct nvk_cmd_buffer *cmd, struct nouveau_copy *copy)
else
P_NV90B5_SET_DST_LAYER(p, 0);
if (nvk_cmd_buffer_device(cmd)->ctx->copy.cls >= 0xc1b5) {
if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_copy >= 0xc1b5) {
P_MTHD(p, NVC1B5, DST_ORIGIN_X);
P_NVC1B5_DST_ORIGIN_X(p, copy->dst.offset_el.x * dst_bw);
P_NVC1B5_DST_ORIGIN_Y(p, copy->dst.offset_el.y);

8
src/nouveau/vulkan/nvk_cmd_dispatch.c
View file

@ -160,7 +160,7 @@ nvk_flush_compute_state(struct nvk_cmd_buffer *cmd,
memset(qmd, 0, sizeof(qmd));
memcpy(qmd, pipeline->qmd_template, sizeof(pipeline->qmd_template));
if (dev->ctx->compute.cls >= AMPERE_COMPUTE_A) {
if (dev->pdev->info.cls_compute >= AMPERE_COMPUTE_A) {
nvc6c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
desc->root.cs.group_count[0],
desc->root.cs.group_count[1],
@ -168,7 +168,7 @@ nvk_flush_compute_state(struct nvk_cmd_buffer *cmd,
nvc6c0_cp_launch_desc_set_cb(qmd, 0, sizeof(desc->root), root_desc_addr);
nvc6c0_cp_launch_desc_set_cb(qmd, 1, sizeof(desc->root), root_desc_addr);
} else if (dev->ctx->compute.cls >= PASCAL_COMPUTE_A) {
} else if (dev->pdev->info.cls_compute >= PASCAL_COMPUTE_A) {
nvc0c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
desc->root.cs.group_count[0],
desc->root.cs.group_count[1],
@ -177,7 +177,7 @@ nvk_flush_compute_state(struct nvk_cmd_buffer *cmd,
nvc0c0_cp_launch_desc_set_cb(qmd, 0, sizeof(desc->root), root_desc_addr);
nvc0c0_cp_launch_desc_set_cb(qmd, 1, sizeof(desc->root), root_desc_addr);
} else {
assert(dev->ctx->compute.cls >= KEPLER_COMPUTE_A);
assert(dev->pdev->info.cls_compute >= KEPLER_COMPUTE_A);
nva0c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
desc->root.cs.group_count[0],
desc->root.cs.group_count[1],
@ -355,7 +355,7 @@ nvk_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
struct nvk_descriptor_state *desc = &cmd->state.cs.descriptors;
/* TODO: Indirect dispatch pre-Turing */
assert(nvk_cmd_buffer_device(cmd)->ctx->eng3d.cls >= TURING_A);
assert(nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A);
desc->root.cs.base_group[0] = 0;
desc->root.cs.base_group[1] = 0;

38
src/nouveau/vulkan/nvk_cmd_draw.c
View file

@ -32,7 +32,7 @@
static inline uint16_t
nvk_cmd_buffer_3d_cls(struct nvk_cmd_buffer *cmd)
{
return nvk_cmd_buffer_device(cmd)->ctx->eng3d.cls;
return nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d;
}
void
@ -84,13 +84,13 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
struct nv_push *p = &push;
/* M2MF state */
if (dev->ctx->m2mf.cls <= FERMI_MEMORY_TO_MEMORY_FORMAT_A) {
if (dev->pdev->info.cls_m2mf <= FERMI_MEMORY_TO_MEMORY_FORMAT_A) {
/* we absolutely do not support Fermi, but if somebody wants to toy
* around with it, this is a must
*/
P_MTHD(p, NV9039, SET_OBJECT);
P_NV9039_SET_OBJECT(p, {
.class_id = dev->ctx->m2mf.cls,
.class_id = dev->pdev->info.cls_m2mf,
.engine_id = 0,
});
}
@ -98,14 +98,14 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
/* 2D state */
P_MTHD(p, NV902D, SET_OBJECT);
P_NV902D_SET_OBJECT(p, {
.class_id = dev->ctx->eng2d.cls,
.class_id = dev->pdev->info.cls_eng2d,
.engine_id = 0,
});
/* 3D state */
P_MTHD(p, NV9097, SET_OBJECT);
P_NV9097_SET_OBJECT(p, {
.class_id = dev->ctx->eng3d.cls,
.class_id = dev->pdev->info.cls_eng3d,
.engine_id = 0,
});
@ -136,7 +136,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
* On older generations we'll let the kernel do it, but starting with GSP we
* have to do it this way.
*/
if (dev->ctx->eng3d.cls >= TURING_A) {
if (dev->pdev->info.cls_eng3d >= TURING_A) {
P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_SET_PRIV_REG));
P_INLINE_DATA(p, 0);
P_INLINE_DATA(p, BITFIELD_BIT(3));
@ -194,7 +194,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
.all_covered_all_hit_once = 0xff,
});
if (dev->ctx->eng3d.cls < VOLTA_A)
if (dev->pdev->info.cls_eng3d < VOLTA_A)
P_IMMD(p, NV9097, SET_ALPHA_FRACTION, 0x3f);
P_IMMD(p, NV9097, CHECK_SPH_VERSION, {
@ -206,7 +206,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
.oldest_supported = 2,
});
if (dev->ctx->eng3d.cls < MAXWELL_A)
if (dev->pdev->info.cls_eng3d < MAXWELL_A)
P_IMMD(p, NV9097, SET_SHADER_SCHEDULING, MODE_OLDEST_THREAD_FIRST);
P_IMMD(p, NV9097, SET_L2_CACHE_CONTROL_FOR_ROP_PREFETCH_READ_REQUESTS,
@ -241,17 +241,17 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
.qualify_by_anti_alias_enable = QUALIFY_BY_ANTI_ALIAS_ENABLE_ENABLE,
});
if (dev->ctx->eng3d.cls < VOLTA_A)
if (dev->pdev->info.cls_eng3d < VOLTA_A)
P_IMMD(p, NV9097, SET_PRIM_CIRCULAR_BUFFER_THROTTLE, 0x3fffff);
P_IMMD(p, NV9097, SET_BLEND_OPT_CONTROL, ALLOW_FLOAT_PIXEL_KILLS_TRUE);
P_IMMD(p, NV9097, SET_BLEND_FLOAT_OPTION, ZERO_TIMES_ANYTHING_IS_ZERO_TRUE);
if (dev->ctx->eng3d.cls < MAXWELL_A)
if (dev->pdev->info.cls_eng3d < MAXWELL_A)
P_IMMD(p, NV9097, SET_MAX_TI_WARPS_PER_BATCH, 3);
if (dev->ctx->eng3d.cls >= KEPLER_A &&
dev->ctx->eng3d.cls < MAXWELL_A) {
if (dev->pdev->info.cls_eng3d >= KEPLER_A &&
dev->pdev->info.cls_eng3d < MAXWELL_A) {
P_IMMD(p, NVA097, SET_TEXTURE_INSTRUCTION_OPERAND,
ORDERING_KEPLER_ORDER);
}
@ -322,7 +322,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
/* OpenGL's GL_POINT_SMOOTH */
P_IMMD(p, NV9097, SET_ANTI_ALIASED_POINT, ENABLE_FALSE);
if (dev->ctx->eng3d.cls >= MAXWELL_B)
if (dev->pdev->info.cls_eng3d >= MAXWELL_B)
P_IMMD(p, NVB197, SET_FILL_VIA_TRIANGLE, MODE_DISABLED);
P_IMMD(p, NV9097, SET_POLY_SMOOTH, ENABLE_FALSE);
@ -334,7 +334,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
.centroid = CENTROID_PER_FRAGMENT,
});
if (dev->ctx->eng3d.cls >= MAXWELL_B) {
if (dev->pdev->info.cls_eng3d >= MAXWELL_B) {
P_IMMD(p, NVB197, SET_OFFSET_RENDER_TARGET_INDEX,
BY_VIEWPORT_INDEX_FALSE);
}
@ -401,8 +401,8 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
P_NV9097_SET_VERTEX_STREAM_SUBSTITUTE_A(p, zero_addr >> 32);
P_NV9097_SET_VERTEX_STREAM_SUBSTITUTE_B(p, zero_addr);
if (dev->ctx->eng3d.cls >= FERMI_A &&
dev->ctx->eng3d.cls < MAXWELL_A) {
if (dev->pdev->info.cls_eng3d >= FERMI_A &&
dev->pdev->info.cls_eng3d < MAXWELL_A) {
assert(dev->vab_memory);
uint64_t vab_addr = dev->vab_memory->offset;
P_MTHD(p, NV9097, SET_VAB_MEMORY_AREA_A);
@ -411,17 +411,17 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
P_NV9097_SET_VAB_MEMORY_AREA_C(p, SIZE_BYTES_256K);
}
if (dev->ctx->eng3d.cls == MAXWELL_A)
if (dev->pdev->info.cls_eng3d == MAXWELL_A)
P_IMMD(p, NVB097, SET_SELECT_MAXWELL_TEXTURE_HEADERS, V_TRUE);
/* Compute state */
P_MTHD(p, NV90C0, SET_OBJECT);
P_NV90C0_SET_OBJECT(p, {
.class_id = dev->ctx->compute.cls,
.class_id = dev->pdev->info.cls_compute,
.engine_id = 0,
});
if (dev->ctx->compute.cls == MAXWELL_COMPUTE_A)
if (dev->pdev->info.cls_compute == MAXWELL_COMPUTE_A)
P_IMMD(p, NVB0C0, SET_SELECT_MAXWELL_TEXTURE_HEADERS, V_TRUE);
return nvk_queue_submit_simple(queue, nv_push_dw_count(&push), push_data,

8
src/nouveau/vulkan/nvk_compute_pipeline.c
View file

@ -203,13 +203,13 @@ nvk_compute_pipeline_create(struct nvk_device *device,
goto fail;
struct nvk_shader *shader = &pipeline->base.shaders[MESA_SHADER_COMPUTE];
if (device->ctx->compute.cls >= AMPERE_COMPUTE_A)
if (device->pdev->info.cls_compute >= AMPERE_COMPUTE_A)
nvc6c0_compute_setup_launch_desc_template(pipeline->qmd_template, shader);
else if (device->ctx->compute.cls >= VOLTA_COMPUTE_A)
else if (device->pdev->info.cls_compute >= VOLTA_COMPUTE_A)
nvc3c0_compute_setup_launch_desc_template(pipeline->qmd_template, shader);
else if (device->ctx->compute.cls >= PASCAL_COMPUTE_A)
else if (device->pdev->info.cls_compute >= PASCAL_COMPUTE_A)
nvc0c0_compute_setup_launch_desc_template(pipeline->qmd_template, shader);
else if (device->ctx->compute.cls >= KEPLER_COMPUTE_A)
else if (device->pdev->info.cls_compute >= KEPLER_COMPUTE_A)
nva0c0_compute_setup_launch_desc_template(pipeline->qmd_template, shader);
else
unreachable("Fermi and older not supported!");

6
src/nouveau/vulkan/nvk_device.c
View file

@ -181,7 +181,7 @@ nvk_CreateDevice(VkPhysicalDevice physicalDevice,
result = nvk_heap_init(dev, &dev->shader_heap,
NOUVEAU_WS_BO_LOCAL, NOUVEAU_WS_BO_WR,
4096 /* overalloc */,
dev->ctx->eng3d.cls < VOLTA_A);
dev->pdev->info.cls_eng3d < VOLTA_A);
if (result != VK_SUCCESS)
goto fail_samplers;
@ -225,8 +225,8 @@ nvk_CreateDevice(VkPhysicalDevice physicalDevice,
memset(zero_map, 0, 0x1000);
nouveau_ws_bo_unmap(dev->zero_page, zero_map);
if (dev->ctx->eng3d.cls >= FERMI_A &&
dev->ctx->eng3d.cls < MAXWELL_A) {
if (dev->pdev->info.cls_eng3d >= FERMI_A &&
dev->pdev->info.cls_eng3d < MAXWELL_A) {
/* max size is 256k */
dev->vab_memory = nouveau_ws_bo_new(dev->pdev->dev, 1 << 17, 1 << 20,
NOUVEAU_WS_BO_LOCAL);

5
src/nouveau/vulkan/nvk_graphics_pipeline.c
View file

@ -1,6 +1,7 @@
#include "nvk_pipeline.h"
#include "nvk_device.h"
#include "nvk_physical_device.h"
#include "nvk_shader.h"
#include "nv_push.h"
#include "vk_nir.h"
@ -379,7 +380,7 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
last_geom = shader;
uint64_t addr = nvk_shader_address(shader);
if (device->ctx->eng3d.cls >= VOLTA_A) {
if (device->pdev->info.cls_eng3d >= VOLTA_A) {
P_MTHD(p, NVC397, SET_PIPELINE_PROGRAM_ADDRESS_A(idx));
P_NVC397_SET_PIPELINE_PROGRAM_ADDRESS_A(p, idx, addr >> 32);
P_NVC397_SET_PIPELINE_PROGRAM_ADDRESS_B(p, idx, addr);
@ -406,7 +407,7 @@ nvk_graphics_pipeline_create(struct nvk_device *device,
P_IMMD(p, NV9097, SET_API_MANDATED_EARLY_Z, shader->fs.early_z);
if (device->ctx->eng3d.cls >= MAXWELL_B) {
if (device->pdev->info.cls_eng3d >= MAXWELL_B) {
P_IMMD(p, NVB197, SET_POST_Z_PS_IMASK,
shader->fs.post_depth_coverage);
} else {

2
src/nouveau/vulkan/nvk_query_pool.c
View file

@ -754,7 +754,7 @@ nvk_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer,
VK_FROM_HANDLE(nvk_buffer, dst_buffer, dstBuffer);
/* TODO: vkCmdCopyQueryPoolResults() with a compute shader */
assert(nvk_cmd_buffer_device(cmd)->ctx->eng3d.cls >= TURING_A);
assert(nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A);
nvk_cmd_buffer_ref_bo(cmd, pool->bo);

8
src/nouveau/vulkan/nvk_queue.c
View file

@ -175,13 +175,13 @@ nvk_queue_state_update(struct nvk_device *dev,
if (qs->shaders.bo) {
/* Compute */
assert(dev->ctx->compute.cls < VOLTA_COMPUTE_A);
assert(dev->pdev->info.cls_compute < VOLTA_COMPUTE_A);
P_MTHD(p, NVA0C0, SET_PROGRAM_REGION_A);
P_NVA0C0_SET_PROGRAM_REGION_A(p, qs->shaders.bo->offset >> 32);
P_NVA0C0_SET_PROGRAM_REGION_B(p, qs->shaders.bo->offset);
/* 3D */
assert(dev->ctx->eng3d.cls < VOLTA_A);
assert(dev->pdev->info.cls_eng3d < VOLTA_A);
P_MTHD(p, NV9097, SET_PROGRAM_REGION_A);
P_NV9097_SET_PROGRAM_REGION_A(p, qs->shaders.bo->offset >> 32);
P_NV9097_SET_PROGRAM_REGION_B(p, qs->shaders.bo->offset);
@ -204,7 +204,7 @@ nvk_queue_state_update(struct nvk_device *dev,
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(p, slm_per_mp);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(p, 0xff);
if (dev->ctx->compute.cls < VOLTA_COMPUTE_A) {
if (dev->pdev->info.cls_compute < VOLTA_COMPUTE_A) {
P_MTHD(p, NVA0C0, SET_SHADER_LOCAL_MEMORY_THROTTLED_A);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(p, slm_per_mp >> 32);
P_NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(p, slm_per_mp);
@ -223,7 +223,7 @@ nvk_queue_state_update(struct nvk_device *dev,
/* We set memory windows unconditionally. Otherwise, the memory window
* might be in a random place and cause us to fault off into nowhere.
*/
if (dev->ctx->compute.cls >= VOLTA_COMPUTE_A) {
if (dev->pdev->info.cls_compute >= VOLTA_COMPUTE_A) {
uint64_t temp = 0xfeULL << 24;
P_MTHD(p, NVC3C0, SET_SHADER_SHARED_MEMORY_WINDOW_A);
P_NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(p, temp >> 32);

7
src/nouveau/vulkan/nvk_sampler.c
View file

@ -1,6 +1,7 @@
#include "nvk_sampler.h"
#include "nvk_device.h"
#include "nvk_physical_device.h"
#include "nouveau_context.h"
#include "util/bitpack_helpers.h"
@ -228,14 +229,14 @@ nvk_CreateSampler(VkDevice device,
unreachable("Invalid mipmap mode");
}
assert(dev->ctx->eng3d.cls >= KEPLER_A);
assert(dev->pdev->info.cls_eng3d >= KEPLER_A);
if (pCreateInfo->flags & VK_SAMPLER_CREATE_NON_SEAMLESS_CUBE_MAP_BIT_EXT) {
SAMP_SET_E(samp, NVA097, 1, CUBEMAP_INTERFACE_FILTERING, USE_WRAP);
} else {
SAMP_SET_E(samp, NVA097, 1, CUBEMAP_INTERFACE_FILTERING, AUTO_SPAN_SEAM);
}
if (dev->ctx->eng3d.cls >= MAXWELL_B) {
if (dev->pdev->info.cls_eng3d >= MAXWELL_B) {
switch (vk_sampler_create_reduction_mode(pCreateInfo)) {
case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE:
SAMP_SET_E(samp, NVB197, 1, REDUCTION_FILTER, RED_NONE);
@ -253,7 +254,7 @@ nvk_CreateSampler(VkDevice device,
SAMP_SET_SF(samp, NV9097, 1, MIP_LOD_BIAS, pCreateInfo->mipLodBias);
assert(dev->ctx->eng3d.cls >= KEPLER_A);
assert(dev->pdev->info.cls_eng3d >= KEPLER_A);
if (pCreateInfo->unnormalizedCoordinates) {
SAMP_SET_E(samp, NVA097, 1, FLOAT_COORD_NORMALIZATION,
FORCE_UNNORMALIZED_COORDS);

8
src/nouveau/vulkan/nvk_shader.c
View file

@ -1167,7 +1167,7 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
{
uint32_t hdr_size = 0;
if (shader->stage != MESA_SHADER_COMPUTE) {
if (dev->ctx->eng3d.cls >= TURING_A)
if (dev->pdev->info.cls_eng3d >= TURING_A)
hdr_size = TU102_SHADER_HEADER_SIZE;
else
hdr_size = GF100_SHADER_HEADER_SIZE;
@ -1176,10 +1176,12 @@ nvk_shader_upload(struct nvk_device *dev, struct nvk_shader *shader)
/* Fermi needs 0x40 alignment
* Kepler+ needs the first instruction to be 0x80 aligned, so we waste 0x30 bytes
*/
int alignment = dev->ctx->eng3d.cls >= KEPLER_A ? 0x80 : 0x40;
int alignment = dev->pdev->info.cls_eng3d >= KEPLER_A ? 0x80 : 0x40;
int offset = 0;
if (dev->ctx->eng3d.cls >= KEPLER_A && dev->ctx->eng3d.cls < TURING_A && hdr_size) {
if (dev->pdev->info.cls_eng3d >= KEPLER_A &&
dev->pdev->info.cls_eng3d < TURING_A &&
hdr_size > 0) {
/* offset will be 0x30 */
offset = alignment - hdr_size;
}