From 08782fbdc3de720d7dae940acc726650343d0e1a Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Tue, 2 Dec 2025 12:20:21 -0800 Subject: [PATCH] tu: Use appropriate chip variants for LRZ reg packing. Part-of: --- src/freedreno/vulkan/tu_clear_blit.cc | 14 +++++----- src/freedreno/vulkan/tu_cmd_buffer.cc | 2 +- src/freedreno/vulkan/tu_lrz.cc | 39 ++++++++++++++------------- 3 files changed, 28 insertions(+), 27 deletions(-) diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index cdcf9aa6052..6b9ba78d13b 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -1399,7 +1399,7 @@ r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, /* Use color format from RB_MRT_BUF_INFO. This register is relevant for * FMT6_NV12_Y. */ - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = fmt)); + tu_cs_emit_regs(cs, GRAS_LRZ_MRT_BUFFER_INFO_0(CHIP, .color_format = fmt)); tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP, .flag_mrts = iview->ubwc_enabled)); tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL()); @@ -1509,8 +1509,8 @@ r3d_dst_gmem(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum a6xx_format color_format = (enum a6xx_format) pkt_field_get( A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT, RB_MRT_BUF_INFO); - tu_cs_emit_regs(cs, - A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = color_format)); + tu_cs_emit_regs( + cs, GRAS_LRZ_MRT_BUFFER_INFO_0(CHIP, .color_format = color_format)); tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP)); tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL()); @@ -1640,12 +1640,12 @@ r3d_setup(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_SRGB_CNTL(util_format_is_srgb(dst_format))); tu_cs_emit_regs(cs, A6XX_SP_SRGB_CNTL(util_format_is_srgb(dst_format))); - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, GRAS_LRZ_CNTL(CHIP, 0)); tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CNTL2(0)); - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO()); + tu_cs_emit_regs(cs, GRAS_LRZ_CNTL2(CHIP, 0)); + tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP)); tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG()); tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG()); @@ -4187,7 +4187,7 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd, .component_enable = COND(clear_rts & (1 << i), 0xf))); } - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0)); + tu_cs_emit_regs(cs, GRAS_LRZ_CNTL(CHIP, 0)); tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0)); tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL()); diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 9d0e0ace468..06de3c74b22 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -784,7 +784,7 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd, A6XX_SP_PS_MRT_REG(i, .dword = 0)); } - tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = mrt0_format)); + tu_cs_emit_regs(cs, GRAS_LRZ_MRT_BUFFER_INFO_0(CHIP, .color_format = mrt0_format)); const bool dither = subpass->legacy_dithering_enabled; const uint32_t dither_cntl = diff --git a/src/freedreno/vulkan/tu_lrz.cc b/src/freedreno/vulkan/tu_lrz.cc index 4d719f965fc..c1bd80bc284 100644 --- a/src/freedreno/vulkan/tu_lrz.cc +++ b/src/freedreno/vulkan/tu_lrz.cc @@ -110,14 +110,13 @@ static void tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image) { if (!depth_image) { - tu_cs_emit_regs(cs, - A6XX_GRAS_LRZ_BUFFER_BASE(0), - A6XX_GRAS_LRZ_BUFFER_PITCH(0), + tu_cs_emit_regs(cs, GRAS_LRZ_BUFFER_BASE(CHIP, 0), + GRAS_LRZ_BUFFER_PITCH(CHIP, 0), A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0)); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO()); - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL()); + tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP)); + tu_cs_emit_regs(cs, GRAS_LRZ_CB_CNTL(CHIP)); } return; @@ -130,18 +129,20 @@ tu6_emit_lrz_buffer(struct tu_cs *cs, struct tu_image *depth_image) lrz_fc_iova = 0; tu_cs_emit_regs( - cs, A6XX_GRAS_LRZ_BUFFER_BASE(.qword = lrz_iova), - A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = depth_image->lrz_layout.lrz_pitch, - .array_pitch = - depth_image->lrz_layout.lrz_layer_size), + cs, GRAS_LRZ_BUFFER_BASE(CHIP, .qword = lrz_iova), + GRAS_LRZ_BUFFER_PITCH( + CHIP, .pitch = depth_image->lrz_layout.lrz_pitch, + .array_pitch = depth_image->lrz_layout.lrz_layer_size), A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(.qword = lrz_fc_iova)); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO( - .depth_format = tu6_pipe2depth(depth_image->vk.format) - )); - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CB_CNTL( - .double_buffer_stride = depth_image->lrz_layout.lrz_buffer_size)); + tu_cs_emit_regs( + cs, GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP, .depth_format = tu6_pipe2depth( + depth_image->vk.format))); + tu_cs_emit_regs( + cs, + GRAS_LRZ_CB_CNTL(CHIP, .double_buffer_stride = + depth_image->lrz_layout.lrz_buffer_size)); } } @@ -167,7 +168,7 @@ tu6_write_lrz_cntl(struct tu_cmd_buffer *cmd, struct tu_cs *cs, { if (CHIP >= A7XX) { /* A7XX split LRZ_CNTL into two seperate registers. */ - struct tu_reg_value cntl2 = A7XX_GRAS_LRZ_CNTL2( + struct tu_reg_value cntl2 = GRAS_LRZ_CNTL2(CHIP, .disable_on_wrong_dir = cntl.disable_on_wrong_dir, .fc_enable = cntl.fc_enable, ); @@ -524,7 +525,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) * CUR_DIR_UNSET. */ if (CHIP >= A7XX) - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(lrz->depth_clear_value.depthStencil.depth)); + tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_CLEAR(CHIP, lrz->depth_clear_value.depthStencil.depth)); tu_emit_event_write(cmd, cs, FD_LRZ_CLEAR); } @@ -704,7 +705,7 @@ tu_lrz_before_sysmem_br(struct tu_cmd_buffer *cmd, struct tu_cs *cs) * dEQP-VK.pipeline.monolithic.color_write_enable.alpha_channel.static.* */ if (lrz->fast_clear) - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(lrz->depth_clear_value.depthStencil.depth)); + tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_CLEAR(CHIP, lrz->depth_clear_value.depthStencil.depth)); } else { /* To workaround the same HW errata as above, but where we don't know * the clear value, copy the clear value from memory to the register. @@ -833,7 +834,7 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) }); if (CHIP >= A7XX) - tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(lrz->depth_clear_value.depthStencil.depth)); + tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_CLEAR(CHIP, lrz->depth_clear_value.depthStencil.depth)); tu_emit_event_write(cmd, &cmd->cs, FD_LRZ_CLEAR); tu_emit_event_write(cmd, &cmd->cs, FD_LRZ_FLUSH); } else { @@ -1007,7 +1008,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd, }); if (CHIP >= A7XX) - tu_cs_emit_regs(&cmd->cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(pDepthStencil->depth)); + tu_cs_emit_regs(&cmd->cs, GRAS_LRZ_DEPTH_CLEAR(CHIP, pDepthStencil->depth)); tu_emit_event_write(cmd, &cmd->cs, FD_LRZ_CLEAR); tu_emit_event_write(cmd, &cmd->cs, FD_LRZ_FLUSH);