fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 02:28:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: Allocate space in the binding table for non-coherent FB fetch.

Browse source 
Unfortunately due to the inconsistent meaning of some surface state
structure fields, we cannot re-use the same binding table entries for
sampling from and rendering into the same set of render buffers, so we
need to allocate a separate binding table block specifically for
render target reads if the non-coherent path is in use.

The slight noise is due to the change of
brw_assign_common_binding_table_offsets to return the next available
binding table index rather than void.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2016-07-01 13:46:40 -07:00
parent 40b23ad57e
commit 08705badfe
4 changed files with 16 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/brw_compiler.h
View file

@ -389,6 +389,7 @@ struct brw_wm_prog_data {
* surface indices the WM-specific surfaces
*/
uint32_t render_target_start;
uint32_t render_target_read_start;
/** @} */
} binding_table;

7
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -1148,7 +1148,7 @@ backend_shader::calculate_cfg()
* unused but also make sure that addition of small offsets to them will
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
void
uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
const struct brw_device_info *devinfo,
const struct gl_shader_program *shader_prog,
@ -1224,9 +1224,10 @@ brw_assign_common_binding_table_offsets(gl_shader_stage stage,
stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
next_binding_table_offset += num_textures;
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
return next_binding_table_offset;
}
static void

2
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -261,7 +261,7 @@ struct brw_gs_compile
unsigned control_data_header_size_bits;
};
void
uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
const struct brw_device_info *devinfo,
const struct gl_shader_program *shader_prog,

13
src/mesa/drivers/dri/i965/brw_wm.c
View file

@ -56,9 +56,16 @@ assign_fs_binding_table_offsets(const struct brw_device_info *devinfo,
prog_data->binding_table.render_target_start = next_binding_table_offset;
next_binding_table_offset += MAX2(key->nr_color_regions, 1);
brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo,
shader_prog, prog, &prog_data->base,
next_binding_table_offset);
next_binding_table_offset =
brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo,
shader_prog, prog, &prog_data->base,
next_binding_table_offset);
if (prog->nir->info.outputs_read && !key->coherent_fb_fetch) {
prog_data->binding_table.render_target_read_start =
next_binding_table_offset;
next_binding_table_offset += key->nr_color_regions;
}
}
/**